📄 ramstart.s
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#/*************************************************************************/
#/* */
#/* FILE VERSION */
#/* */
#/* ramstart.s S3C44B0X 1.00 */
#/* */
#/* Project name: UCLinux Boot Loader for S3C44B0X Main board */
#/* Description: */
#/* Board initialization codes */
#/* -- Configure Memory */
#/* -- Initialize Ports */
#/* -- ISR */
#/* -- Stacks */
#/* */
#/* AUTHOR */
#/* */
#/* ShangJun,Liu */
#/* DATE: */
#/* 2003-06-07 */
#/* */
#/* HISTORY */
#/* */
#/* NAME DATE REMARKS */
#/* ShangJun Liu 2003-06-06 13:10 */
#/* ShangJun Liu 2003-10-22 08:25 */
#/*************************************************************************/
#/*************************************************************************/
#/* Constant Definitions */
#/* I/O PORT */
#/*************************************************************************/
.equ rBWSCON , 0x01C80000 /* bus width and wait status control */
.equ rBANKCON0 , 0x01C80004 /* Boot ROM Control */
.equ rBANKCON1 , 0x01C80008 /* BANK1 Control */
.equ rBANKCON2 , 0x01C8000c /* BANK2 Control */
.equ rBANKCON3 , 0x01C80010 /* BANK3 Control */
.equ rBANKCON4 , 0x01C80014 /* BANK4 Control */
.equ rBANKCON5 , 0x01C80018 /* BANK5 Control */
.equ rBANKCON6 , 0x01C8001c /* BANK6 Control */
.equ rBANKCON7 , 0x01C80020 /* BANK7 Control */
.equ rREFRESH , 0x01C80024 /* DRAM/SDRAM Refresh Control */
.equ rBANKSIZE , 0x01C80028 /* Flexible Bank Size */
.equ rMRSRB6 , 0x01C8002c /* Mode Register set for SDRAM */
.equ rMRSRB7 , 0x01C80030 /* Mode Register set for SDRAM */
.equ rPCONA , 0x01d20000 /* Port A */
.equ rPDATA , 0x01d20004
.equ rPCONB , 0x01d20008 /* Port B */
.equ rPDATB , 0x01d2000c
.equ rPCONC , 0x01d20010 /* Port C */
.equ rPDATC , 0x01d20014
.equ rPUPC , 0x01d20018
.equ rPCOND , 0x01d2001c /* Port D */
.equ rPDATD , 0x01d20020
.equ rPUPD , 0x01d20024
.equ rPCONE , 0x01d20028 /* Port E */
.equ rPDATE , 0x01d2002c
.equ rPUPE , 0x01d20030
.equ rPCONF , 0x01d20034 /* Port F */
.equ rPDATF , 0x01d20038
.equ rPUPF , 0x01d2003c
.equ rPCONG , 0x01d20040 /* Port G */
.equ rPDATG , 0x01d20044
.equ rPUPG , 0x01d20048
.equ rSPUCR , 0x01d2004c /* Special Pull-Up Registor Control Register */
.equ rEXTINT , 0x01d20050 /* External Interrupt Control Register */
#/*************************************************************************/
#/* Constant Definitions */
#/* Interrupt Control */
#/*************************************************************************/
.equ INTCON , 0x01e00000
.equ INTPND , 0x01e00004
.equ INTMOD , 0x01e00008
.equ INTMSK , 0x01e0000c
.equ I_ISPR , 0x01e00020
.equ I_CMST , 0x01e0001c
.equ I_PMST , 0x01e00014
#/*************************************************************************/
#/* Constant Definitions */
#/* Watchdog timer */
#/*************************************************************************/
.equ WTCON , 0x01d30000
#/*************************************************************************/
#/* Constant Definitions */
#/* Clock Controller */
#/*************************************************************************/
.equ PLLCON , 0x01d80000
.equ CLKCON , 0x01d80004
.equ LOCKTIME , 0x01d8000c
#/*************************************************************************/
#/* Constant Definitions */
#/* Memory Controller */
#/*************************************************************************/
.equ REFRESH , 0x01c80024
#/*************************************************************************/
#/* Constant Definitions */
#/* System configuration */
#/*************************************************************************/
.equ SYSCFG , 0x01c00000
.equ NCACHBE0 , 0x01c00004
.equ NCACHBE1 , 0x01c00008
#/*************************************************************************/
#/* Constant Definitions */
#/* Pre-defined constants */
#/*************************************************************************/
.equ USERMODE , 0x10
.equ FIQMODE , 0x11
.equ IRQMODE , 0x12
.equ SVCMODE , 0x13
.equ ABORTMODE , 0x17
.equ UNDEFMODE , 0x1b
.equ MODEMASK , 0x1f
.equ NOINT , 0xc0
.equ TIMER0_INT , 0x00002000
.equ LOCKOUT , 0xC0 /* Interrupt lockout value */
.equ LOCK_MSK , 0xC0 /* Interrupt lockout mask value */
.equ MODE_MASK , 0x1F /* Processor Mode Mask */
.equ SUP_MODE , 0x13 /* Supervisor Mode (SVC) */
.equ VECTOR_TABLE , 0x0c032000 /* just 16M Bytes SDRAM. */
.equ VIRTUAL_TABLE , 0x0c032000 /* just 16M Bytes SDRAM. */
.equ _ISR_STARTADDRESS , 0x0c7fff00 /*GCS6(nSCS0):16MByte SDRAM */
#/*************************************************************************/
#/* Import Modules */
#/*************************************************************************/
.extern Image_ZI_Base
.extern Image_ZI_Limit
.extern Image_RO_Base
.extern Image_RO_Limit
.extern Image_RW_Base
.extern Main
.extern copy_code_to_ram
#/*************************************************************************/
#/* Entry of target */
#/*************************************************************************/
# ENTRY
__entry :
b ResetHandler /* Reset vector */
b HandlerUndef /* Undefined instruction */
b HandlerSWI /* SWI */
b HandlerPabort /* Prefetch abort */
b HandlerDabort /* Data abort */
b . /* Address exception */
b HandlerIRQ /* IRQ */
b HandlerFIQ /* FIQ */
#/*************************************************************************/
#/* Entry of FIQ interrupt */
#/*************************************************************************/
HandlerFIQ:
sub sp,sp,#4
stmfd sp!,{r0}
ldr r0,=HandleFIQ
ldr r0,[r0]
str r0,[sp,#4]
ldmfd sp!,{r0,pc}
#/*************************************************************************/
#/* Entry of IRQ interrupt */
#/*************************************************************************/
HandlerIRQ:
sub sp,sp,#4
stmfd sp!,{r0}
ldr r0,=HandleIRQ
ldr r0,[r0]
str r0,[sp,#4]
ldmfd sp!,{r0,pc}
#/*************************************************************************/
#/* Entry of Undefined instruction interrupt */
#/*************************************************************************/
HandlerUndef:
sub sp,sp,#4
stmfd sp!,{r0}
ldr r0,=HandleUndef
ldr r0,[r0]
str r0,[sp,#4]
ldmfd sp!,{r0,pc}
#/*************************************************************************/
#/* Entry of SWI interrupt */
#/*************************************************************************/
HandlerSWI:
sub sp,sp,#4
stmfd sp!,{r0}
ldr r0,=HandleSWI
ldr r0,[r0]
str r0,[sp,#4]
ldmfd sp!,{r0,pc}
#/*************************************************************************/
#/* Entry of Data abort interrupt */
#/*************************************************************************/
HandlerDabort:
sub sp,sp,#4
stmfd sp!,{r0}
ldr r0,=HandleDabort
ldr r0,[r0]
str r0,[sp,#4]
ldmfd sp!,{r0,pc}
#/*************************************************************************/
#/* Entry of Prefetch abort interrupt */
#/*************************************************************************/
HandlerPabort:
sub sp,sp,#4
stmfd sp!,{r0}
ldr r0,=HandlePabort
ldr r0,[r0]
str r0,[sp,#4]
ldmfd sp!,{r0,pc}
IsrIRQ: /*using I_ISPR register.*/
sub lr,lr,#4
stmfd sp!,{lr} /* save the return pc */
stmfd sp!,{r0-r4} /* save r0-r4 */
sub sp,sp,#4 /* to be used by isr pc */
stmfd sp!,{r8-r9} /* save r8-r9 */
ldr r9,=I_ISPR /* distribute the irq */
ldr r9,[r9]
cmp r9, #0x0
beq i2
mov r8,#0x0
i0: /* check every bit */
movs r9,r9,lsr #1
bcs i1
add r8,r8,#4
b i0 /* next bit */
i1: /* one interrupt trigged*/
ldr r9,=HandleADC /* isr vector base address */
add r9,r9,r8 /* compute the offset */
ldr r9,[r9] /* obtain the isr address */
str r9,[sp,#8] /* restore to the isr pc of sp*/
mov lr,pc /* return to 'ldmfd sp!,{r0-r4, pc}^' */
ldmfd sp!,{r8-r9,pc} /* restore r8-r9, call isr and return */
ldmfd sp!,{r0-r4, pc}^/* restore r0-r4 and return */
i2:
ldmfd sp!,{r8-r9} /* restore the r8-r9 */
add sp,sp,#4 /* isr pc */
ldmfd sp!,{r0-r4, pc}^/* restore r0-r4 and return */
#/*************************************************************************/
#/* Entry of reset vector interrupt */
#/*************************************************************************/
ResetHandler :
#/*************************************************************************/
#/* */
#/* FUNCTION */
#/* */
#/* main_entry */
#/* */
#/* DESCRIPTION */
#/* */
#/* This function is the entry function of target */
#/* */
#/* - HardWare Initialization */
#/* - Configuration Port control registers */
#/* - Set clock control registers */
#/* - Set memory control registers (every CS control) */
#/* - init stack */
#/* - Set memory control registers (every CS control) */
#/* - Clear the un-initialized global and static */
#/* C data areas */
#/* - Move the initialized global and initialized */
#/* C data areas */
#/* - Initialize the vector table */
#/* - Jump to Main function */
#/* */
#/* AUTHOR */
#/* */
#/* ShangJun,Liu */
#/* DATE: */
#/* 2003-06-05 */
#/* CALLED BY */
#/* */
#/* */
#/* CALLS */
#/* */
#/* none */
#/* */
#/* INPUTS */
#/* */
#/* None */
#/* */
#/* OUTPUTS */
#/* */
#/* None */
#/* */
#/* HISTORY */
#/* */
#/* NAME DATE REMARKS */
#/* */
#/* */
#/*************************************************************************/
#VOID main_entry(void)
#{
.global main_entry
main_entry :
#
# Disable interrupt and switch to supervisor mode
#
MRS a1,CPSR /*; Pickup current CPSR*/
BIC a1,a1,#MODE_MASK /*; Clear the mode bits*/
ORR a1,a1,#SUP_MODE /*; Set the supervisor mode bits*/
ORR a1,a1,#LOCKOUT /*; Insure IRQ and FIQ intr are locked out*/
MSR CPSR_cxsf,a1 /*; Setup the new CPSR*/
#
# HardWare Initialization.
# disable all interrupt
#
ldr r0,=INTCON /*#Interrupt control register. */
ldr r1,=0x07 /*#non-vectored mode,disable IRQ,disable FIQ. */
str r1,[r0]
ldr r0,=INTMSK /*#Interrupt MASK register. */
ldr r1,=0x07ffffff /*#disable all(30) interrupt sources.*/
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