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📄 ramstart.s

📁 武汉创维特ARM7实验箱的全部源代码
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#/*************************************************************************/
#/*                                                                       */
#/*     FILE                                        VERSION               */
#/*                                                                       */
#/*      ramstart.s                              S3C44B0X 1.00            */
#/*                                                                       */
#/* Description:				                                          */
#/*	     Board initialization codes     	                              */
#/*	                    --  Configure Memory                              */
#/*                     --  Initialize Ports                              */
#/*                     --  ISR                                           */
#/*                     --  Stacks                                        */
#/*                                                                       */
#/* AUTHOR                                                                */
#/*                                                                       */
#/*      ShangJun,Liu                                                     */
#/* DATE:                                                                 */
#/*      2001-06-07                                                       */
#/*                                                                       */
#/* HISTORY                                                               */
#/*                                                                       */
#/*         NAME            DATE                    REMARKS               */
#/*         ShangJun Liu    2001-06-06 13:10                              */
#/*************************************************************************/


.include "ramstart.inc"

#/*************************************************************************/
#/* Import Modules                                                        */
#/*************************************************************************/
	.extern	Image_ZI_Base
	.extern	Image_ZI_Limit
	.extern	Image_RO_Base
	.extern	Image_RO_Limit
	.extern	Image_RW_Base
	.extern Main
	.extern IsrIRQ
	
#/*************************************************************************/
#/* Entry of target                                                       */
#/*************************************************************************/
#		ENTRY
__entry :
		b       ResetHandler                /* Reset vector          */
		b       HandlerUndef                /* Undefined instruction */
		b       HandlerSWI		            /* SWI                   */
		b       HandlerPabort        		/* Prefetch abort        */
		b       HandlerDabort          		/* Data abort            */
		b       HandlerAbort            	/* Address exception     */
		b       HandlerIRQ           		/* IRQ                   */
		b		HandlerFIQ           		/* FIQ                   */

/* Entry of Undefined instruction interrupt                          */
HandlerUndef:

/* Entry of SWI interrupt                                            */
HandlerSWI:

/* Entry of Prefetch abort interrupt                                 */
HandlerPabort:

/* Entry of Prefetch abort interrupt                                 */
HandlerAbort:

/* Entry of Data abort interrupt                                     */
HandlerDabort:

/* Entry of FIQ interrupt                                            */
HandlerFIQ:
        b		.		

#/*************************************************************************/
#/* Entry of IRQ interrupt                                                */
#/*************************************************************************/
HandlerIRQ:
        sub     sp,sp,#4
        stmfd   sp!,{r0}
        ldr     r0,=HandleIRQ
        ldr     r0,[r0]			
        str     r0,[sp,#4]
        ldmfd   sp!,{r0,pc}

#/*************************************************************************/
#/* Entry of reset vector interrupt                                       */
#/*************************************************************************/
ResetHandler :
#VOID    main_entry(void)
#{
	.global	main_entry
main_entry :	

#
# Disable interrupt and switch to supervisor mode
#
		MRS		a1,CPSR				    /*; Pickup current CPSR*/
		BIC		a1,a1,#MODE_MASK		/*; Clear the mode bits*/
		ORR		a1,a1,#SUP_MODE			/*; Set the supervisor mode bits*/
		ORR		a1,a1,#LOCKOUT			/*; Insure IRQ and FIQ intr are locked out*/
		MSR		CPSR_cxsf,a1			/*; Setup the new CPSR*/
#
# HardWare Initialization.
# disable all interrupt
#
   		ldr    r0,=INTCON	    /*#Interrupt control register. */
    	ldr    r1,=0x07         /*#non-vectored mode,disable IRQ,disable FIQ.  */		
    	str    r1,[r0]

   		ldr    r0,=INTMSK	    /*#Interrupt MASK register. */
    	ldr    r1,=0x07ffffff   /*#disable all(30) interrupt sources.*/  		
    	str    r1,[r0]


    	ldr    r0,=WTCON	    /*#watch dog disable*/ 
    	ldr    r1,=0x0 		
    	str    r1,[r0]

#/*************************************************************************/
#/* Initialize stacks                                                     */
#/*************************************************************************/
    	ldr		sp, =SVCStack	
   		bl		InitStacks   

#/*************************************************************************/
#/* Call startram -- Run at sdram from this inst                          */
#/*************************************************************************/
		LDR		pc, = startram	
		
#/*************************************************************************/
#/* Clear the un-initialized global and static C data areas               */
#/*************************************************************************/
#{  
startram :
		LDR		a1,=Image_ZI_Base	/* Pickup the start of the BSS area */     
		MOV		a3,#0				/* Clear value in a3 */                    
		LDR		a2,=Image_ZI_Limit	/* Pickup the end of the BSS area */       
		CMP		a1,a2                                                           
		BEQ		move_data                                                       
clear_loop :                                                                 
		STR		a3,[a1],#4				/* Clear a word, a1 += 4 */                
		CMP		a1,a2					/* end of ZI ?  */                         
		BNE		clear_loop				/* If not, continue with the BSS clear */  
#                                                                            
# Move the initialized global and initialized C data areas                   
#                                                                            
move_data :                                                                   
		LDR		a1,=Image_RW_Base	/* Pickup the start of the DATA area  */   
		LDR		a2,=Image_RO_Limit	/* Pickup the start of the DATA storage  */
		LDR		a3,=Image_ZI_Base	/* Pickup the end of the BSS area  */      
		                                                                        
		CMP		a1,a3                                                           
		BEQ		goto_main                                                       
		                                                                        
move_loop :                                                                    
		LDR		a4,[a2],#4                                                      
		STR		a4,[a1],#4				/* move a word, a1 += 4, a2 += 4 */        
		CMP		a1,a3					/* end of DATA ?   */                      
		BNE		move_loop				/* If not, continue with the BSS clear  */ 
                                                                             
goto_main :                                                                    
		BL      Main    	

#/*************************************************************************/
#/* The function for initializing stack                                   */
#/*************************************************************************/
InitStacks:
    	mrs    r0,cpsr					
    	
    	bic    r0,r0,#MODEMASK|NOINT
    	
    	orr    r1,r0,#IRQMODE|NOINT
    	msr    cpsr_cxsf,r1 	    	/*;IRQMode*/
    	ldr    sp,=IRQStack             
		
    	orr    r1,r0,#SVCMODE
    	msr    cpsr_cxsf,r1 	    	/*;SVCMode*/
    	ldr    sp,=SVCStack      	
    	
    	mov    pc,lr /*;The LR register may be not valid for the mode changes.*/
    			
.END	
	
	
	

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