📄 ramstart.s
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ldr r1,=0x0
str r1,[r0]
ldr r0,=SYSCFG /*#enable writer buffer, full cache enable, stall disable */
ldr r1,=0xE
str r1,[r0]
ldr r0,=NCACHBE0 /*#non cacheable area control*/
ldr r1,=0xb0000000 /*#bank0,1,2,3,4,5 area*/
str r1,[r0]
ldr r0,=NCACHBE1 /*#non cacheable area control*/
ldr r1,=0xc000c000
str r1,[r0]
# just start to change SW code from here, according to samsung demo board.
#****************************************************
#* Configuration Port control registers *
#****************************************************
#==== PORT A GROUP ====
#ADDR24 ADDR23 ADDR22 ADDR21 ADDR20 ADDR19 ADDR18 ADDR17 ADDR16 ADDR0
# 1, 1, 1, 1, 1, 1, 1, 1, 1, 1
ldr r1,=rPCONA
ldr r0,=0x3ff
str r0,[r1]
#==== PORT B GROUP ====
#nGCS0 - FLASH
#nGCS1 - 74HC244 AND 74HC273
#nGCS2 - CS8900A
#nGCS3 - PDIUSBD12
#nGCS4 - SEG7
#nGCS5 -
#nSCS6 - SDRAM
#nGCS5 nGCS4 nGCS3 nGCS2 nGCS1 nWBE3 nWBE2 nSRAS nSCAS SCLK SCKE
# 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1
ldr r1,=rPCONB
ldr r0,=0x7ff
str r0,[r1]
#==== PORT C GROUP ====
# nCTS0 nRTS0 OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT VD4 VD5 VD6 VD7 IISCLK IISDI IISDO IISLRCK
# 11 11 01 01 01 01 01 01 11 11 11 11 11 11 11 11
ldr r1,=rPCONC
ldr r0,=0xf555ffff
str r0,[r1]
ldr r1,=rPUPC
ldr r0,=0x00ff /*#pc[8~15] PULL-UP*/
str r0,[r1]
ldr r1,=rPDATC /*lcd on;led on*/
ldr r0,=0xeeff
str r0,[r1]
#==== PORT D GROUP ====
#VFRAME VM VLINE VCLK VD3 VD2 VD1 VD0 (LCD/MODE)
#10 10 10 10 10 10 10 10
ldr r1,=rPCOND
ldr r0,=0xaaaa
str r0,[r1]
ldr r1,=rPUPD
ldr r0,=0xff /*#disable PULL-UP*/
str r0,[r1]
#==== PORT E GROUP ====
# CODECLK OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT TOUT0 RXD0 TXD0 FOUT OUT
# 10 01 01 01 01 01 10 10 11
ldr r1,=rPCONE
ldr r0,=0x255ab
str r0,[r1]
ldr r1,=rPDATE
ldr r0,=0x0f /*output = 0*/
str r0,[r1]
ldr r1,=rPUPE
ldr r0,=0x0
str r0,[r1]
#==== PORT F GROUP ====
#nCTS1 RXD1 TXD1 nRTS1 nXDREQ0 nXDACK0 nWAIT OUTPUT OUTPUT
#010 010 010 010 11 11 10 01 01
ldr r1,=rPCONF
ldr r0,=0x124be9
str r0,[r1]
ldr r1,=rPUPF
ldr r0,=0xff /*disable PULL-UP*/
str r0,[r1]
#==== PORT G GROUP ====
#OUTPUT OUTPUT OUTPUT EINT4 EINT3 EINT2 EINT1 EINT0
#01 01 01 11 11 11 11 11
ldr r1,=rPCONG
ldr r0,=0x57ff
str r0,[r1]
ldr r1,=rPUPG
ldrb r0,=0x00 /*# all pull up and only input pin work*/
strb r0,[r1]
#***************
#* SET ETC *
#***************
ldr r1,=rSPUCR /*#DATA BUS pull-up disable*/
ldrb r0,=0x7
strb r0,[r1]
#EINT7 EINT6 EINT5 EINT4 EINT3 EINT2 EINT1 EINT0
# ------ falling edge ------
#000 000 000 100 010 100 010 010
ldr r1,=rEXTINT /*# EINT2,3,4 falling edge*/
ldr r0,=0x42422
str r0,[r1]
ldr r0,=INTMSK
ldr r1,=0x07ffffff /*#all interrupt disable*/
str r1,[r0]
#****************************************************
#* Set clock control registers *
#****************************************************
ldr r0,=LOCKTIME
ldr r1,=800 /*# EX) count = t_lock * Fin (t_lock=200us, Fin=10MHz) = 2000*/
str r1,[r0]
ldr r0,=PLLCON /*#temporary setting of PLL*/
ldr r1, =0x34031 /*#Fin=10MHz,Fout=60MHz,*/
str r1,[r0]
ldr r0,=CLKCON
ldr r1,=0x7fd8
str r1,[r0]
ldr r0,=rBWSCON /*#BWSCON Address*/
ldr r1,=0x11000100
str r1,[r0]
ldr r0,=rBANKCON0
ldr r1,=0x700
str r1,[r0]
ldr r0,=rBANKCON1
ldr r1,=0x700 /* 0x7ffc */
str r1,[r0]
ldr r0,=rBANKCON2
ldr r1,=0x700 /* 0x7ffc */
str r1,[r0]
ldr r0,=rBANKCON3
ldr r1,=0x7568
str r1,[r0]
ldr r0,=rBANKCON4
ldr r1,=0x700 /* 0x7ffc */
str r1,[r0]
ldr r0,=rBANKCON5
ldr r1,=0x700 /* 0x7ffc */
str r1,[r0]
ldr r0,=rBANKCON6
ldr r1,=0x18008
str r1,[r0]
ldr r0,=rBANKCON7
ldr r1,=0x18000
str r1,[r0]
ldr r0,=rREFRESH
ldr r1,=0xac03e1
str r1,[r0]
ldr r0,=rBANKSIZE
ldr r1,=0x16
str r1,[r0]
ldr r0,=rMRSRB6
ldr r1,=0x020
str r1,[r0]
ldr r0,=rMRSRB7
ldr r1,=0x020
str r1,[r0]
#/*************************************************************************/
#/* Initialize stacks */
#/*************************************************************************/
ldr sp, =SVCStack
bl InitStacks
#;/*************************************************************************/
#;/* Clear the un-initialized global and static C data areas */
#;/*************************************************************************/
#;{
LDR a1,=Image_ZI_Base /*#; Pickup the start of the BSS area*/
MOV a3,#0 /*#; Clear value in a3 */
LDR a2,=Image_ZI_Limit /*#; Pickup the end of the BSS area */
CMP a1,a2
BEQ move_data
clear_loop :
STR a3,[a1],#4 /* Clear a word, a1 += 4 */
CMP a1,a2 /* end of ZI ? */
BNE clear_loop /* If not, continue with the BSS clear */
#
# Move the initialized global and initialized C data areas
#
move_data :
LDR a1,=Image_RW_Base /* Pickup the start of the DATA area */
LDR a2,=Image_RO_Limit /* Pickup the start of the DATA storage */
LDR a3,=Image_ZI_Base /* Pickup the end of the BSS area */
CMP a1,a3
BEQ goto_main
move_loop :
LDR a4,[a2],#4
STR a4,[a1],#4 /* move a word, a1 += 4, a2 += 4 */
CMP a1,a3 /* end of DATA ? */
BNE move_loop /* If not, continue with the BSS clear */
goto_main :
BL Main
#/*************************************************************************/
#/* The function for initializing stack */
#/*************************************************************************/
InitStacks:
mrs r0,cpsr
bic r0,r0,#MODEMASK /*;r0 AND NOT MODEMASK -> r0 (MODEMASK = 0x1f) */
/*;r0 OR UNDEFMODE|NOINT -> r1 */
orr r1,r0,#UNDEFMODE|NOINT /*UndefMode*/
msr cpsr_cxsf,r1
ldr sp,=UndefStack
orr r1,r0,#ABORTMODE|NOINT /*;AbortMode*/
msr cpsr_cxsf,r1
ldr sp,=AbortStack
orr r1,r0,#IRQMODE|NOINT
msr cpsr_cxsf,r1 /*;IRQMode*/
ldr sp,=IRQStack
orr r1,r0,#FIQMODE|NOINT
msr cpsr_cxsf,r1 /*;FIQMode*/
ldr sp,=FIQStack
bic r0,r0,#MODEMASK|0x80
orr r1,r0,#SVCMODE
msr cpsr_cxsf,r1 /*;SVCMode*/
ldr sp,=SVCStack
mov pc,lr /*;The LR register may be not valid for the mode changes.*/
# Stack Area
.EQU SVCStack , _ISR_STARTADDRESS - 0xc00 @ 0xC7FF100
.EQU UserStack , _ISR_STARTADDRESS - 0x600 @ 0xC7FF900
.EQU UndefStack , _ISR_STARTADDRESS - 0x500 @ 0xC7FFA00
.EQU AbortStack , _ISR_STARTADDRESS - 0x400 @ 0xC7FFB00
.EQU IRQStack , _ISR_STARTADDRESS @ 0xC7FFF00
.EQU FIQStack , _ISR_STARTADDRESS @ 0xC7FFF00
# ISR Vector
.EQU HandleReset , _ISR_STARTADDRESS
.EQU HandleUndef , _ISR_STARTADDRESS + 0x04
.EQU HandleSWI , _ISR_STARTADDRESS + 0x08
.EQU HandlePabort , _ISR_STARTADDRESS + 0x0c
.EQU HandleDabort , _ISR_STARTADDRESS + 0x10
.EQU HandleReserved , _ISR_STARTADDRESS + 0x14
.EQU HandleIRQ , _ISR_STARTADDRESS + 0x18
.EQU HandleFIQ , _ISR_STARTADDRESS + 0x1c
.EQU HandleADC , _ISR_STARTADDRESS + 0x20
.EQU HandleRTC , _ISR_STARTADDRESS + 0x24
.EQU HandleUTXD1 , _ISR_STARTADDRESS + 0x28
.EQU HandleUTXD0 , _ISR_STARTADDRESS + 0x2c
.EQU HandleSIO , _ISR_STARTADDRESS + 0x30
.EQU HandleIIC , _ISR_STARTADDRESS + 0x34
.EQU HandleURXD1 , _ISR_STARTADDRESS + 0x38
.EQU HandleURXD0 , _ISR_STARTADDRESS + 0x3c
.EQU HandleTIMER5 , _ISR_STARTADDRESS + 0x40
.EQU HandleTIMER4 , _ISR_STARTADDRESS + 0x44
.EQU HandleTIMER3 , _ISR_STARTADDRESS + 0x48
.EQU HandleTIMER2 , _ISR_STARTADDRESS + 0x4c
.EQU HandleTIMER1 , _ISR_STARTADDRESS + 0x50
.EQU HandleTIMER0 , _ISR_STARTADDRESS + 0x54
.EQU HandleUERR01 , _ISR_STARTADDRESS + 0x58
.EQU HandleWDT , _ISR_STARTADDRESS + 0x5c
.EQU HandleBDMA1 , _ISR_STARTADDRESS + 0x60
.EQU HandleBDMA0 , _ISR_STARTADDRESS + 0x64
.EQU HandleZDMA1 , _ISR_STARTADDRESS + 0x68
.EQU HandleZDMA0 , _ISR_STARTADDRESS + 0x6c
.EQU HandleTICK , _ISR_STARTADDRESS + 0x70
.EQU HandleEINT4567 , _ISR_STARTADDRESS + 0x74
.EQU HandleEINT3 , _ISR_STARTADDRESS + 0x78
.EQU HandleEINT2 , _ISR_STARTADDRESS + 0x7c
.EQU HandleEINT1 , _ISR_STARTADDRESS + 0x80
.EQU HandleEINT0 , _ISR_STARTADDRESS + 0x84
.END
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