pcu_e.c

uboot200903最新版本的通用uboot

static long int dram_size (long int mamr_value, long int *base,
			   long int maxsize)
{
	volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
	volatile memctl8xx_t *memctl = &immr->im_memctl;

	memctl->memc_mamr = mamr_value;

	return (get_ram_size (base, maxsize));
}

/* ------------------------------------------------------------------------- */

#if PCU_E_WITH_SWAPPED_CS	/* XXX */
#define	ETH_CFG_BITS	(CONFIG_SYS_PB_ETH_CFG1 | CONFIG_SYS_PB_ETH_CFG2  | CONFIG_SYS_PB_ETH_CFG3 )
#else  /* XXX */
#define	ETH_CFG_BITS	(CONFIG_SYS_PB_ETH_MDDIS | CONFIG_SYS_PB_ETH_CFG1 | \
			 CONFIG_SYS_PB_ETH_CFG2  | CONFIG_SYS_PB_ETH_CFG3 )
#endif /* XXX */

#define ETH_ALL_BITS	(ETH_CFG_BITS | CONFIG_SYS_PB_ETH_POWERDOWN | CONFIG_SYS_PB_ETH_RESET)

void reset_phy (void)
{
	immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
	ulong value;

	/* Configure all needed port pins for GPIO */
#if PCU_E_WITH_SWAPPED_CS	/* XXX */
# ifdef CONFIG_SYS_ETH_MDDIS_VALUE
	immr->im_ioport.iop_padat |= CONFIG_SYS_PA_ETH_MDDIS;
# else
	immr->im_ioport.iop_padat &= ~(CONFIG_SYS_PA_ETH_MDDIS);	/* Set low */
# endif
	immr->im_ioport.iop_papar &= ~(CONFIG_SYS_PA_ETH_MDDIS);	/* GPIO */
	immr->im_ioport.iop_paodr &= ~(CONFIG_SYS_PA_ETH_MDDIS);	/* active output */
	immr->im_ioport.iop_padir |= CONFIG_SYS_PA_ETH_MDDIS;	/* output */
#endif /* XXX */
	immr->im_cpm.cp_pbpar &= ~(ETH_ALL_BITS);	/* GPIO */
	immr->im_cpm.cp_pbodr &= ~(ETH_ALL_BITS);	/* active output */

	value = immr->im_cpm.cp_pbdat;

	/* Assert Powerdown and Reset signals */
	value |= CONFIG_SYS_PB_ETH_POWERDOWN;
	value &= ~(CONFIG_SYS_PB_ETH_RESET);

	/* PHY configuration includes MDDIS and CFG1 ... CFG3 */
#if !PCU_E_WITH_SWAPPED_CS
# ifdef CONFIG_SYS_ETH_MDDIS_VALUE
	value |= CONFIG_SYS_PB_ETH_MDDIS;
# else
	value &= ~(CONFIG_SYS_PB_ETH_MDDIS);
# endif
#endif
#ifdef CONFIG_SYS_ETH_CFG1_VALUE
	value |= CONFIG_SYS_PB_ETH_CFG1;
#else
	value &= ~(CONFIG_SYS_PB_ETH_CFG1);
#endif
#ifdef CONFIG_SYS_ETH_CFG2_VALUE
	value |= CONFIG_SYS_PB_ETH_CFG2;
#else
	value &= ~(CONFIG_SYS_PB_ETH_CFG2);
#endif
#ifdef CONFIG_SYS_ETH_CFG3_VALUE
	value |= CONFIG_SYS_PB_ETH_CFG3;
#else
	value &= ~(CONFIG_SYS_PB_ETH_CFG3);
#endif

	/* Drive output signals to initial state */
	immr->im_cpm.cp_pbdat = value;
	immr->im_cpm.cp_pbdir |= ETH_ALL_BITS;
	udelay (10000);

	/* De-assert Ethernet Powerdown */
	immr->im_cpm.cp_pbdat &= ~(CONFIG_SYS_PB_ETH_POWERDOWN);	/* Enable PHY power */
	udelay (10000);

	/* de-assert RESET signal of PHY */
	immr->im_cpm.cp_pbdat |= CONFIG_SYS_PB_ETH_RESET;
	udelay (1000);
}

/*-----------------------------------------------------------------------
 * Board Special Commands: access functions for "PUMA" FPGA
 */
#if defined(CONFIG_CMD_BSP)

#define	PUMA_READ_MODE	0
#define PUMA_LOAD_MODE	1

int do_puma (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
{
	ulong addr, len;

	switch (argc) {
	case 2:		/* PUMA reset */
		if (strncmp (argv[1], "stat", 4) == 0) {	/* Reset */
			puma_status ();
			return 0;
		}
		break;
	case 4:		/* PUMA load addr len */
		if (strcmp (argv[1], "load") != 0)
			break;

		addr = simple_strtoul (argv[2], NULL, 16);
		len = simple_strtoul (argv[3], NULL, 16);

		printf ("PUMA load: addr %08lX len %ld (0x%lX):  ",
			addr, len, len);
		puma_load (addr, len);

		return 0;
	default:
		break;
	}
	cmd_usage(cmdtp);
	return 1;
}

U_BOOT_CMD (puma, 4, 1, do_puma,
	    "access PUMA FPGA",
	    "status - print PUMA status\n"
	    "puma load addr len - load PUMA configuration data\n");

#endif

/* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */

static void puma_set_mode (int mode)
{
	volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
	volatile memctl8xx_t *memctl = &immr->im_memctl;

	/* disable PUMA in memory controller */
#if PCU_E_WITH_SWAPPED_CS	/* XXX */
	memctl->memc_br3 = 0;
#else  /* XXX */
	memctl->memc_br4 = 0;
#endif /* XXX */

	switch (mode) {
	case PUMA_READ_MODE:
#if PCU_E_WITH_SWAPPED_CS	/* XXX */
		memctl->memc_or3 = PUMA_CONF_OR_READ;
		memctl->memc_br3 = PUMA_CONF_BR_READ;
#else  /* XXX */
		memctl->memc_or4 = PUMA_CONF_OR_READ;
		memctl->memc_br4 = PUMA_CONF_BR_READ;
#endif /* XXX */
		break;
	case PUMA_LOAD_MODE:
#if PCU_E_WITH_SWAPPED_CS	/* XXX */
		memctl->memc_or3 = PUMA_CONF_OR_LOAD;
		memctl->memc_br3 = PUMA_CONF_BR_LOAD;
#else  /* XXX */
		memctl->memc_or4 = PUMA_CONF_OR_READ;
		memctl->memc_br4 = PUMA_CONF_BR_READ;
#endif /* XXX */
		break;
	}
}

/* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */

#define	PUMA_INIT_TIMEOUT	1000	/* max. 1000 ms = 1 second */

static void puma_load (ulong addr, ulong len)
{
	volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
	volatile uchar *fpga_addr = (volatile uchar *) PUMA_CONF_BASE;	/* XXX ??? */
	uchar *data = (uchar *) addr;
	int i;

	/* align length */
	if (len & 1)
		++len;

	/* Reset FPGA */
	immr->im_ioport.iop_pcpar &= ~(CONFIG_SYS_PC_PUMA_INIT);	/* make input */
	immr->im_ioport.iop_pcso  &= ~(CONFIG_SYS_PC_PUMA_INIT);
	immr->im_ioport.iop_pcdir &= ~(CONFIG_SYS_PC_PUMA_INIT);

#if PCU_E_WITH_SWAPPED_CS	/* XXX */
	immr->im_cpm.cp_pbpar &= ~(CONFIG_SYS_PB_PUMA_PROG);		/* GPIO */
	immr->im_cpm.cp_pbodr &= ~(CONFIG_SYS_PB_PUMA_PROG);		/* active output */
	immr->im_cpm.cp_pbdat &= ~(CONFIG_SYS_PB_PUMA_PROG);		/* Set low */
	immr->im_cpm.cp_pbdir |=   CONFIG_SYS_PB_PUMA_PROG;		/* output */
#else
	immr->im_ioport.iop_papar &= ~(CONFIG_SYS_PA_PUMA_PROG);	/* GPIO */
	immr->im_ioport.iop_padat &= ~(CONFIG_SYS_PA_PUMA_PROG);	/* Set low */
	immr->im_ioport.iop_paodr &= ~(CONFIG_SYS_PA_PUMA_PROG);	/* active output */
	immr->im_ioport.iop_padir |=   CONFIG_SYS_PA_PUMA_PROG;	/* output */
#endif /* XXX */
	udelay (100);

#if PCU_E_WITH_SWAPPED_CS	/* XXX */
	immr->im_cpm.cp_pbdat |= CONFIG_SYS_PB_PUMA_PROG;	/* release reset */
#else
	immr->im_ioport.iop_padat |= CONFIG_SYS_PA_PUMA_PROG;	/* release reset */
#endif /* XXX */

	/* wait until INIT indicates completion of reset */
	for (i = 0; i < PUMA_INIT_TIMEOUT; ++i) {
		udelay (1000);
		if (immr->im_ioport.iop_pcdat & CONFIG_SYS_PC_PUMA_INIT)
			break;
	}
	if (i == PUMA_INIT_TIMEOUT) {
		printf ("*** PUMA init timeout ***\n");
		return;
	}

	puma_set_mode (PUMA_LOAD_MODE);

	while (len--)
		*fpga_addr = *data++;

	puma_set_mode (PUMA_READ_MODE);

	puma_status ();
}

/* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */

static void puma_status (void)
{
	/* Check state */
	printf ("PUMA initialization is %scomplete\n",
		puma_init_done ()? "" : "NOT ");
}

/* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */

static int puma_init_done (void)
{
	volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;

	/* make sure pin is GPIO input */
	immr->im_ioport.iop_pcpar &= ~(CONFIG_SYS_PC_PUMA_DONE);
	immr->im_ioport.iop_pcso &= ~(CONFIG_SYS_PC_PUMA_DONE);
	immr->im_ioport.iop_pcdir &= ~(CONFIG_SYS_PC_PUMA_DONE);

	return (immr->im_ioport.iop_pcdat & CONFIG_SYS_PC_PUMA_DONE) ? 1 : 0;
}

/* ------------------------------------------------------------------------- */

int misc_init_r (void)
{
	ulong addr = 0;
	ulong len = 0;
	char *s;

	printf ("PUMA:  ");
	if (puma_init_done ()) {
		printf ("initialized\n");
		return 0;
	}

	if ((s = getenv ("puma_addr")) != NULL)
		addr = simple_strtoul (s, NULL, 16);

	if ((s = getenv ("puma_len")) != NULL)
		len = simple_strtoul (s, NULL, 16);

	if ((!addr) || (!len)) {
		printf ("net list undefined\n");
		return 0;
	}

	printf ("loading... ");

	puma_load (addr, len);
	return (0);
}

/* ------------------------------------------------------------------------- */