📄 reg_ebi.h
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#define EBI_DEV2_TIM1_WR2_OFFS 0x00000230#define EBI_DEV2_TIM1_WR2(base) ((base) + EBI_DEV2_TIM1_WR2_OFFS)#define EBI_DEV2_TIM_EXT_OFFS 0x00000234#define EBI_DEV2_TIM_EXT(base) ((base) + EBI_DEV2_TIM_EXT_OFFS)#define EBI_DEV2_TIM2_CFI_RD1_OFFS 0x00000238#define EBI_DEV2_TIM2_CFI_RD1(base) ((base) + EBI_DEV2_TIM2_CFI_RD1_OFFS)#define EBI_DEV2_TIM2_CFI_RD2_OFFS 0x0000023C#define EBI_DEV2_TIM2_CFI_RD2(base) ((base) + EBI_DEV2_TIM2_CFI_RD2_OFFS)#define EBI_DEV2_TIM3_DMA1_OFFS 0x00000240#define EBI_DEV2_TIM3_DMA1(base) ((base) + EBI_DEV2_TIM3_DMA1_OFFS)#define EBI_DEV2_TIM3_DMA2_OFFS 0x00000244#define EBI_DEV2_TIM3_DMA2(base) ((base) + EBI_DEV2_TIM3_DMA2_OFFS)#define EBI_DEV2_TIM4_UDMA1_OFFS 0x00000248#define EBI_DEV2_TIM4_UDMA1(base) ((base) + EBI_DEV2_TIM4_UDMA1_OFFS)#define EBI_DEV2_TIM4_UDMA2_OFFS 0x0000024C#define EBI_DEV2_TIM4_UDMA2(base) ((base) + EBI_DEV2_TIM4_UDMA2_OFFS)#define EBI_DEV2_ACK_RM_CNT_OFFS 0x00000250#define EBI_DEV2_ACK_RM_CNT(base) ((base) + EBI_DEV2_ACK_RM_CNT_OFFS)#define EBI_DEV3_DMA_EXT_ADDR_OFFS 0x00000300#define EBI_DEV3_DMA_EXT_ADDR(base) ((base) + EBI_DEV3_DMA_EXT_ADDR_OFFS)#define EBI_DEV3_EXT_ACC_OFFS 0x00000304#define EBI_DEV3_EXT_ACC(base) ((base) + EBI_DEV3_EXT_ACC_OFFS)#define EBI_DEV3_CONFIG1_OFFS 0x00000308#define EBI_DEV3_CONFIG1(base) ((base) + EBI_DEV3_CONFIG1_OFFS)#define EBI_DEV3_CONFIG2_OFFS 0x0000030C#define EBI_DEV3_CONFIG2(base) ((base) + EBI_DEV3_CONFIG2_OFFS)#define EBI_DEV3_FIFO_CONFIG_OFFS 0x00000310#define EBI_DEV3_FIFO_CONFIG(base) ((base) + EBI_DEV3_FIFO_CONFIG_OFFS)#define EBI_DEV3_FLASH_CONF_ST_OFFS 0x00000314#define EBI_DEV3_FLASH_CONF_ST(base) ((base) + EBI_DEV3_FLASH_CONF_ST_OFFS)#define EBI_DEV3_DMA_CONFIG1_OFFS 0x00000318#define EBI_DEV3_DMA_CONFIG1(base) ((base) + EBI_DEV3_DMA_CONFIG1_OFFS)#define EBI_DEV3_DMA_CONFIG2_OFFS 0x0000031C#define EBI_DEV3_DMA_CONFIG2(base) ((base) + EBI_DEV3_DMA_CONFIG2_OFFS)#define EBI_DEV3_DMA_ECC_CTRL_OFFS 0x00000320#define EBI_DEV3_DMA_ECC_CTRL(base) ((base) + EBI_DEV3_DMA_ECC_CTRL_OFFS)#define EBI_DEV3_TIM1_RD1_OFFS 0x00000324#define EBI_DEV3_TIM1_RD1(base) ((base) + EBI_DEV3_TIM1_RD1_OFFS)#define EBI_DEV3_TIM1_RD2_OFFS 0x00000328#define EBI_DEV3_TIM1_RD2(base) ((base) + EBI_DEV3_TIM1_RD2_OFFS)#define EBI_DEV3_TIM1_WR1_OFFS 0x0000032C#define EBI_DEV3_TIM1_WR1(base) ((base) + EBI_DEV3_TIM1_WR1_OFFS)#define EBI_DEV3_TIM1_WR2_OFFS 0x00000330#define EBI_DEV3_TIM1_WR2(base) ((base) + EBI_DEV3_TIM1_WR2_OFFS)#define EBI_DEV3_TIM_EXT_OFFS 0x00000334#define EBI_DEV3_TIM_EXT(base) ((base) + EBI_DEV3_TIM_EXT_OFFS)#define EBI_DEV3_TIM2_CFI_RD1_OFFS 0x00000338#define EBI_DEV3_TIM2_CFI_RD1(base) ((base) + EBI_DEV3_TIM2_CFI_RD1_OFFS)#define EBI_DEV3_TIM2_CFI_RD2_OFFS 0x0000033C#define EBI_DEV3_TIM2_CFI_RD2(base) ((base) + EBI_DEV3_TIM2_CFI_RD2_OFFS)#define EBI_DEV3_TIM3_DMA1_OFFS 0x00000340#define EBI_DEV3_TIM3_DMA1(base) ((base) + EBI_DEV3_TIM3_DMA1_OFFS)#define EBI_DEV3_TIM3_DMA2_OFFS 0x00000344#define EBI_DEV3_TIM3_DMA2(base) ((base) + EBI_DEV3_TIM3_DMA2_OFFS)#define EBI_DEV3_TIM4_UDMA1_OFFS 0x00000348#define EBI_DEV3_TIM4_UDMA1(base) ((base) + EBI_DEV3_TIM4_UDMA1_OFFS)#define EBI_DEV3_TIM4_UDMA2_OFFS 0x0000034C#define EBI_DEV3_TIM4_UDMA2(base) ((base) + EBI_DEV3_TIM4_UDMA2_OFFS)#define EBI_DEV3_ACK_RM_CNT_OFFS 0x00000350#define EBI_DEV3_ACK_RM_CNT(base) ((base) + EBI_DEV3_ACK_RM_CNT_OFFS)#define EBI_DEV4_DMA_EXT_ADDR_OFFS 0x00000400#define EBI_DEV4_DMA_EXT_ADDR(base) ((base) + EBI_DEV4_DMA_EXT_ADDR_OFFS)#define EBI_DEV4_EXT_ACC_OFFS 0x00000404#define EBI_DEV4_EXT_ACC(base) ((base) + EBI_DEV4_EXT_ACC_OFFS)#define EBI_DEV4_CONFIG1_OFFS 0x00000408#define EBI_DEV4_CONFIG1(base) ((base) + EBI_DEV4_CONFIG1_OFFS)#define EBI_DEV4_CONFIG2_OFFS 0x0000040C#define EBI_DEV4_CONFIG2(base) ((base) + EBI_DEV4_CONFIG2_OFFS)#define EBI_DEV4_FIFO_CONFIG_OFFS 0x00000410#define EBI_DEV4_FIFO_CONFIG(base) ((base) + EBI_DEV4_FIFO_CONFIG_OFFS)#define EBI_DEV4_FLASH_CONF_ST_OFFS 0x00000414#define EBI_DEV4_FLASH_CONF_ST(base) ((base) + EBI_DEV4_FLASH_CONF_ST_OFFS)#define EBI_DEV4_DMA_CONFIG1_OFFS 0x00000418#define EBI_DEV4_DMA_CONFIG1(base) ((base) + EBI_DEV4_DMA_CONFIG1_OFFS)#define EBI_DEV4_DMA_CONFIG2_OFFS 0x0000041C#define EBI_DEV4_DMA_CONFIG2(base) ((base) + EBI_DEV4_DMA_CONFIG2_OFFS)#define EBI_DEV4_DMA_ECC_CTRL_OFFS 0x00000420#define EBI_DEV4_DMA_ECC_CTRL(base) ((base) + EBI_DEV4_DMA_ECC_CTRL_OFFS)#define EBI_DEV4_TIM1_RD1_OFFS 0x00000424#define EBI_DEV4_TIM1_RD1(base) ((base) + EBI_DEV4_TIM1_RD1_OFFS)#define EBI_DEV4_TIM1_RD2_OFFS 0x00000428#define EBI_DEV4_TIM1_RD2(base) ((base) + EBI_DEV4_TIM1_RD2_OFFS)#define EBI_DEV4_TIM1_WR1_OFFS 0x0000042C#define EBI_DEV4_TIM1_WR1(base) ((base) + EBI_DEV4_TIM1_WR1_OFFS)#define EBI_DEV4_TIM1_WR2_OFFS 0x00000430#define EBI_DEV4_TIM1_WR2(base) ((base) + EBI_DEV4_TIM1_WR2_OFFS)#define EBI_DEV4_TIM_EXT_OFFS 0x00000434#define EBI_DEV4_TIM_EXT(base) ((base) + EBI_DEV4_TIM_EXT_OFFS)#define EBI_DEV4_TIM2_CFI_RD1_OFFS 0x00000438#define EBI_DEV4_TIM2_CFI_RD1(base) ((base) + EBI_DEV4_TIM2_CFI_RD1_OFFS)#define EBI_DEV4_TIM2_CFI_RD2_OFFS 0x0000043C#define EBI_DEV4_TIM2_CFI_RD2(base) ((base) + EBI_DEV4_TIM2_CFI_RD2_OFFS)#define EBI_DEV4_TIM3_DMA1_OFFS 0x00000440#define EBI_DEV4_TIM3_DMA1(base) ((base) + EBI_DEV4_TIM3_DMA1_OFFS)#define EBI_DEV4_TIM3_DMA2_OFFS 0x00000444#define EBI_DEV4_TIM3_DMA2(base) ((base) + EBI_DEV4_TIM3_DMA2_OFFS)#define EBI_DEV4_TIM4_UDMA1_OFFS 0x00000448#define EBI_DEV4_TIM4_UDMA1(base) ((base) + EBI_DEV4_TIM4_UDMA1_OFFS)#define EBI_DEV4_TIM4_UDMA2_OFFS 0x0000044C#define EBI_DEV4_TIM4_UDMA2(base) ((base) + EBI_DEV4_TIM4_UDMA2_OFFS)#define EBI_DEV4_ACK_RM_CNT_OFFS 0x00000450#define EBI_DEV4_ACK_RM_CNT(base) ((base) + EBI_DEV4_ACK_RM_CNT_OFFS)#define EBI_INTERLEAVE_CNT_OFFS 0x00000900#define EBI_INTERLEAVE_CNT(base) ((base) + EBI_INTERLEAVE_CNT_OFFS)#define EBI_CNT_FL_PROGR_OFFS 0x00000904#define EBI_CNT_FL_PROGR(base) ((base) + EBI_CNT_FL_PROGR_OFFS)#define EBI_CNT_EXT_PAGE_SZ_OFFS 0x0000090C#define EBI_CNT_EXT_PAGE_SZ(base) ((base) + EBI_CNT_EXT_PAGE_SZ_OFFS)#define EBI_CNT_WAIT_RDY_OFFS 0x00000914#define EBI_CNT_WAIT_RDY(base) ((base) + EBI_CNT_WAIT_RDY_OFFS)#define EBI_CNT_ACK_OFFS 0x00000918#define EBI_CNT_ACK(base) ((base) + EBI_CNT_ACK_OFFS)#define EBI_GENIO1_CONFIG1_OFFS 0x00000A00#define EBI_GENIO1_CONFIG1(base) ((base) + EBI_GENIO1_CONFIG1_OFFS)#define EBI_GENIO1_CONFIG2_OFFS 0x00000A04#define EBI_GENIO1_CONFIG2(base) ((base) + EBI_GENIO1_CONFIG2_OFFS)#define EBI_GENIO1_CONFIG3_OFFS 0x00000A08#define EBI_GENIO1_CONFIG3(base) ((base) + EBI_GENIO1_CONFIG3_OFFS)#define EBI_GENIO2_CONFIG1_OFFS 0x00000A10#define EBI_GENIO2_CONFIG1(base) ((base) + EBI_GENIO2_CONFIG1_OFFS)#define EBI_GENIO2_CONFIG2_OFFS 0x00000A14#define EBI_GENIO2_CONFIG2(base) ((base) + EBI_GENIO2_CONFIG2_OFFS)#define EBI_GENIO2_CONFIG3_OFFS 0x00000A18#define EBI_GENIO2_CONFIG3(base) ((base) + EBI_GENIO2_CONFIG3_OFFS)#define EBI_GENIO3_CONFIG1_OFFS 0x00000A20#define EBI_GENIO3_CONFIG1(base) ((base) + EBI_GENIO3_CONFIG1_OFFS)#define EBI_GENIO3_CONFIG2_OFFS 0x00000A24#define EBI_GENIO3_CONFIG2(base) ((base) + EBI_GENIO3_CONFIG2_OFFS)#define EBI_GENIO3_CONFIG3_OFFS 0x00000A28#define EBI_GENIO3_CONFIG3(base) ((base) + EBI_GENIO3_CONFIG3_OFFS)#define EBI_GENIO4_CONFIG1_OFFS 0x00000A30#define EBI_GENIO4_CONFIG1(base) ((base) + EBI_GENIO4_CONFIG1_OFFS)#define EBI_GENIO4_CONFIG2_OFFS 0x00000A34#define EBI_GENIO4_CONFIG2(base) ((base) + EBI_GENIO4_CONFIG2_OFFS)#define EBI_GENIO4_CONFIG3_OFFS 0x00000A38#define EBI_GENIO4_CONFIG3(base) ((base) + EBI_GENIO4_CONFIG3_OFFS)#define EBI_GENIO5_CONFIG1_OFFS 0x00000A40#define EBI_GENIO5_CONFIG1(base) ((base) + EBI_GENIO5_CONFIG1_OFFS)#define EBI_GENIO5_CONFIG2_OFFS 0x00000A44#define EBI_GENIO5_CONFIG2(base) ((base) + EBI_GENIO5_CONFIG2_OFFS)#define EBI_GENIO5_CONFIG3_OFFS 0x00000A48#define EBI_GENIO5_CONFIG3(base) ((base) + EBI_GENIO5_CONFIG3_OFFS)#endif⌨️ 快捷键说明
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