adsp-edn-extended_def.h

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#define SPORT1_TCLKDIV                 0xFFC00908 /* SPORT1 Transmit Clock Divider */
#define SPORT1_TFSDIV                  0xFFC0090C /* SPORT1 Transmit Frame Sync Divider */
#define SPORT1_TX                      0xFFC00910 /* SPORT1 TX Data Register */
#define SPORT1_RX                      0xFFC00918 /* SPORT1 RX Data Register */
#define SPORT1_RCR1                    0xFFC00920 /* SPORT1 Transmit Configuration 1 Register */
#define SPORT1_RCR2                    0xFFC00924 /* SPORT1 Transmit Configuration 2 Register */
#define SPORT1_RCLKDIV                 0xFFC00928 /* SPORT1 Receive Clock Divider */
#define SPORT1_RFSDIV                  0xFFC0092C /* SPORT1 Receive Frame Sync Divider */
#define SPORT1_STAT                    0xFFC00930 /* SPORT1 Status Register */
#define SPORT1_CHNL                    0xFFC00934 /* SPORT1 Current Channel Register */
#define SPORT1_MCMC1                   0xFFC00938 /* SPORT1 Multi-Channel Configuration Register 1 */
#define SPORT1_MCMC2                   0xFFC0093C /* SPORT1 Multi-Channel Configuration Register 2 */
#define DMA0_NEXT_DESC_PTR             0xFFC00C00
#define DMA0_START_ADDR                0xFFC00C04
#define DMA0_CONFIG                    0xFFC00C08 /* DMA Channel 0 Configuration Register */
#define DMA0_X_COUNT                   0xFFC00C10
#define DMA0_X_MODIFY                  0xFFC00C14
#define DMA0_Y_COUNT                   0xFFC00C18
#define DMA0_Y_MODIFY                  0xFFC00C1C
#define DMA0_CURR_DESC_PTR             0xFFC00C20
#define DMA0_CURR_ADDR                 0xFFC00C24
#define DMA0_IRQ_STATUS                0xFFC00C28
#define DMA0_PERIPHERAL_MAP            0xFFC00C2C
#define DMA0_CURR_X_COUNT              0xFFC00C30
#define DMA0_CURR_Y_COUNT              0xFFC00C38
#define DMA1_NEXT_DESC_PTR             0xFFC00C40
#define DMA1_START_ADDR                0xFFC00C44
#define DMA1_CONFIG                    0xFFC00C48 /* DMA Channel 1 Configuration Register */
#define DMA1_X_COUNT                   0xFFC00C50
#define DMA1_X_MODIFY                  0xFFC00C54
#define DMA1_Y_COUNT                   0xFFC00C58
#define DMA1_Y_MODIFY                  0xFFC00C5C
#define DMA1_CURR_DESC_PTR             0xFFC00C60
#define DMA1_CURR_ADDR                 0xFFC00C64
#define DMA1_IRQ_STATUS                0xFFC00C68
#define DMA1_PERIPHERAL_MAP            0xFFC00C6C
#define DMA1_CURR_X_COUNT              0xFFC00C70
#define DMA1_CURR_Y_COUNT              0xFFC00C78
#define DMA2_NEXT_DESC_PTR             0xFFC00C80
#define DMA2_START_ADDR                0xFFC00C84
#define DMA2_CONFIG                    0xFFC00C88 /* DMA Channel 2 Configuration Register */
#define DMA2_X_COUNT                   0xFFC00C90
#define DMA2_X_MODIFY                  0xFFC00C94
#define DMA2_Y_COUNT                   0xFFC00C98
#define DMA2_Y_MODIFY                  0xFFC00C9C
#define DMA2_CURR_DESC_PTR             0xFFC00CA0
#define DMA2_CURR_ADDR                 0xFFC00CA4
#define DMA2_IRQ_STATUS                0xFFC00CA8
#define DMA2_PERIPHERAL_MAP            0xFFC00CAC
#define DMA2_CURR_X_COUNT              0xFFC00CB0
#define DMA2_CURR_Y_COUNT              0xFFC00CB8
#define DMA3_NEXT_DESC_PTR             0xFFC00CC0
#define DMA3_START_ADDR                0xFFC00CC4
#define DMA3_CONFIG                    0xFFC00CC8 /* DMA Channel 3 Configuration Register */
#define DMA3_X_COUNT                   0xFFC00CD0
#define DMA3_X_MODIFY                  0xFFC00CD4
#define DMA3_Y_COUNT                   0xFFC00CD8
#define DMA3_Y_MODIFY                  0xFFC00CDC
#define DMA3_CURR_DESC_PTR             0xFFC00CE0
#define DMA3_CURR_ADDR                 0xFFC00CE4
#define DMA3_IRQ_STATUS                0xFFC00CE8
#define DMA3_PERIPHERAL_MAP            0xFFC00CEC
#define DMA3_CURR_X_COUNT              0xFFC00CF0
#define DMA3_CURR_Y_COUNT              0xFFC00CF8
#define DMA4_NEXT_DESC_PTR             0xFFC00D00
#define DMA4_START_ADDR                0xFFC00D04
#define DMA4_CONFIG                    0xFFC00D08 /* DMA Channel 4 Configuration Register */
#define DMA4_X_COUNT                   0xFFC00D10
#define DMA4_X_MODIFY                  0xFFC00D14
#define DMA4_Y_COUNT                   0xFFC00D18
#define DMA4_Y_MODIFY                  0xFFC00D1C
#define DMA4_CURR_DESC_PTR             0xFFC00D20
#define DMA4_CURR_ADDR                 0xFFC00D24
#define DMA4_IRQ_STATUS                0xFFC00D28
#define DMA4_PERIPHERAL_MAP            0xFFC00D2C
#define DMA4_CURR_X_COUNT              0xFFC00D30
#define DMA4_CURR_Y_COUNT              0xFFC00D38
#define DMA5_NEXT_DESC_PTR             0xFFC00D40
#define DMA5_START_ADDR                0xFFC00D44
#define DMA5_CONFIG                    0xFFC00D48 /* DMA Channel 5 Configuration Register */
#define DMA5_X_COUNT                   0xFFC00D50
#define DMA5_X_MODIFY                  0xFFC00D54
#define DMA5_Y_COUNT                   0xFFC00D58
#define DMA5_Y_MODIFY                  0xFFC00D5C
#define DMA5_CURR_DESC_PTR             0xFFC00D60
#define DMA5_CURR_ADDR                 0xFFC00D64
#define DMA5_IRQ_STATUS                0xFFC00D68
#define DMA5_PERIPHERAL_MAP            0xFFC00D6C
#define DMA5_CURR_X_COUNT              0xFFC00D70
#define DMA5_CURR_Y_COUNT              0xFFC00D78
#define DMA6_NEXT_DESC_PTR             0xFFC00D80
#define DMA6_START_ADDR                0xFFC00D84
#define DMA6_CONFIG                    0xFFC00D88 /* DMA Channel 6 Configuration Register */
#define DMA6_X_COUNT                   0xFFC00D90
#define DMA6_X_MODIFY                  0xFFC00D94
#define DMA6_Y_COUNT                   0xFFC00D98
#define DMA6_Y_MODIFY                  0xFFC00D9C
#define DMA6_CURR_DESC_PTR             0xFFC00DA0
#define DMA6_CURR_ADDR                 0xFFC00DA4
#define DMA6_IRQ_STATUS                0xFFC00DA8
#define DMA6_PERIPHERAL_MAP            0xFFC00DAC
#define DMA6_CURR_X_COUNT              0xFFC00DB0
#define DMA6_CURR_Y_COUNT              0xFFC00DB8
#define DMA7_NEXT_DESC_PTR             0xFFC00DC0
#define DMA7_START_ADDR                0xFFC00DC4
#define DMA7_CONFIG                    0xFFC00DC8 /* DMA Channel 7 Configuration Register */
#define DMA7_X_COUNT                   0xFFC00DD0
#define DMA7_X_MODIFY                  0xFFC00DD4
#define DMA7_Y_COUNT                   0xFFC00DD8
#define DMA7_Y_MODIFY                  0xFFC00DDC
#define DMA7_CURR_DESC_PTR             0xFFC00DE0
#define DMA7_CURR_ADDR                 0xFFC00DE4
#define DMA7_IRQ_STATUS                0xFFC00DE8
#define DMA7_PERIPHERAL_MAP            0xFFC00DEC
#define DMA7_CURR_X_COUNT              0xFFC00DF0
#define DMA7_CURR_Y_COUNT              0xFFC00DF8
#define MDMA_D0_NEXT_DESC_PTR          0xFFC00E00
#define MDMA_D0_START_ADDR             0xFFC00E04
#define MDMA_D0_CONFIG                 0xFFC00E08
#define MDMA_D0_X_COUNT                0xFFC00E10
#define MDMA_D0_X_MODIFY               0xFFC00E14
#define MDMA_D0_Y_COUNT                0xFFC00E18
#define MDMA_D0_Y_MODIFY               0xFFC00E1C
#define MDMA_D0_CURR_DESC_PTR          0xFFC00E20
#define MDMA_D0_CURR_ADDR              0xFFC00E24
#define MDMA_D0_IRQ_STATUS             0xFFC00E28
#define MDMA_D0_PERIPHERAL_MAP         0xFFC00E2C
#define MDMA_D0_CURR_X_COUNT           0xFFC00E30
#define MDMA_D0_CURR_Y_COUNT           0xFFC00E38
#define MDMA_S0_NEXT_DESC_PTR          0xFFC00E40
#define MDMA_S0_START_ADDR             0xFFC00E44
#define MDMA_S0_CONFIG                 0xFFC00E48
#define MDMA_S0_X_COUNT                0xFFC00E50
#define MDMA_S0_X_MODIFY               0xFFC00E54
#define MDMA_S0_Y_COUNT                0xFFC00E58
#define MDMA_S0_Y_MODIFY               0xFFC00E5C
#define MDMA_S0_CURR_DESC_PTR          0xFFC00E60
#define MDMA_S0_CURR_ADDR              0xFFC00E64
#define MDMA_S0_IRQ_STATUS             0xFFC00E68
#define MDMA_S0_PERIPHERAL_MAP         0xFFC00E6C
#define MDMA_S0_CURR_X_COUNT           0xFFC00E70
#define MDMA_S0_CURR_Y_COUNT           0xFFC00E78
#define MDMA_D1_NEXT_DESC_PTR          0xFFC00E80
#define MDMA_D1_START_ADDR             0xFFC00E84
#define MDMA_D1_CONFIG                 0xFFC00E88 /* MemDMA Stream 1 Destination Configuration Register */
#define MDMA_D1_X_COUNT                0xFFC00E90
#define MDMA_D1_X_MODIFY               0xFFC00E94
#define MDMA_D1_Y_COUNT                0xFFC00E98
#define MDMA_D1_Y_MODIFY               0xFFC00E9C
#define MDMA_D1_CURR_DESC_PTR          0xFFC00EA0
#define MDMA_D1_CURR_ADDR              0xFFC00EA4
#define MDMA_D1_IRQ_STATUS             0xFFC00EA8
#define MDMA_D1_PERIPHERAL_MAP         0xFFC00EAC
#define MDMA_D1_CURR_X_COUNT           0xFFC00EB0
#define MDMA_D1_CURR_Y_COUNT           0xFFC00EB8
#define MDMA_S1_NEXT_DESC_PTR          0xFFC00EC0
#define MDMA_S1_START_ADDR             0xFFC00EC4
#define MDMA_S1_CONFIG                 0xFFC00EC8
#define MDMA_S1_X_COUNT                0xFFC00ED0
#define MDMA_S1_X_MODIFY               0xFFC00ED4
#define MDMA_S1_Y_COUNT                0xFFC00ED8
#define MDMA_S1_Y_MODIFY               0xFFC00EDC
#define MDMA_S1_CURR_DESC_PTR          0xFFC00EE0
#define MDMA_S1_CURR_ADDR              0xFFC00EE4
#define MDMA_S1_IRQ_STATUS             0xFFC00EE8
#define MDMA_S1_PERIPHERAL_MAP         0xFFC00EEC
#define MDMA_S1_CURR_X_COUNT           0xFFC00EF0
#define MDMA_S1_CURR_Y_COUNT           0xFFC00EF8
#define EBIU_AMGCTL                    0xFFC00A00
#define EBIU_AMBCTL0                   0xFFC00A04
#define EBIU_AMBCTL1                   0xFFC00A08
#define EBIU_SDGCTL                    0xFFC00A10
#define EBIU_SDBCTL                    0xFFC00A14
#define EBIU_SDRRC                     0xFFC00A18
#define EBIU_SDSTAT                    0xFFC00A1C
#define DMA_TC_CNT                     0xFFC00B0C
#define DMA_TC_PER                     0xFFC00B10

#endif /* __BFIN_DEF_ADSP_EDN_extended__ */