adsp-edn-extended_def.h

uboot200903最新版本的通用uboot

#define DMAFLX4_XCOUNT                 0xFFC00D10
#define DMAFLX4_XMODIFY                0xFFC00D14
#define DMAFLX4_YCOUNT                 0xFFC00D18
#define DMAFLX4_YMODIFY                0xFFC00D1C
#define DMAFLX4_IRQSTAT                0xFFC00D28
#define DMAFLX4_PMAP                   0xFFC00D2C
#define DMAFLX4_CURXCOUNT              0xFFC00D30
#define DMAFLX4_CURYCOUNT              0xFFC00D38
#define DMAFLX5_DMACNFG                0xFFC00D48
#define DMAFLX5_XCOUNT                 0xFFC00D50
#define DMAFLX5_XMODIFY                0xFFC00D54
#define DMAFLX5_YCOUNT                 0xFFC00D58
#define DMAFLX5_YMODIFY                0xFFC00D5C
#define DMAFLX5_IRQSTAT                0xFFC00D68
#define DMAFLX5_PMAP                   0xFFC00D6C
#define DMAFLX5_CURXCOUNT              0xFFC00D70
#define DMAFLX5_CURYCOUNT              0xFFC00D78
#define DMAFLX6_DMACNFG                0xFFC00D88
#define DMAFLX6_XCOUNT                 0xFFC00D90
#define DMAFLX6_XMODIFY                0xFFC00D94
#define DMAFLX6_YCOUNT                 0xFFC00D98
#define DMAFLX6_YMODIFY                0xFFC00D9C
#define DMAFLX6_IRQSTAT                0xFFC00DA8
#define DMAFLX6_PMAP                   0xFFC00DAC
#define DMAFLX6_CURXCOUNT              0xFFC00DB0
#define DMAFLX6_CURYCOUNT              0xFFC00DB8
#define DMAFLX7_DMACNFG                0xFFC00DC8
#define DMAFLX7_XCOUNT                 0xFFC00DD0
#define DMAFLX7_XMODIFY                0xFFC00DD4
#define DMAFLX7_YCOUNT                 0xFFC00DD8
#define DMAFLX7_YMODIFY                0xFFC00DDC
#define DMAFLX7_IRQSTAT                0xFFC00DE8
#define DMAFLX7_PMAP                   0xFFC00DEC
#define DMAFLX7_CURXCOUNT              0xFFC00DF0
#define DMAFLX7_CURYCOUNT              0xFFC00DF8
#define TIMER0_CONFIG                  0xFFC00600
#define TIMER0_COUNTER                 0xFFC00604
#define TIMER0_PERIOD                  0xFFC00608
#define TIMER0_WIDTH                   0xFFC0060C
#define TIMER1_CONFIG                  0xFFC00610
#define TIMER1_COUNTER                 0xFFC00614
#define TIMER1_PERIOD                  0xFFC00618
#define TIMER1_WIDTH                   0xFFC0061C
#define TIMER2_CONFIG                  0xFFC00620
#define TIMER2_COUNTER                 0xFFC00624
#define TIMER2_PERIOD                  0xFFC00628
#define TIMER2_WIDTH                   0xFFC0062C
#define TIMER_ENABLE                   0xFFC00640
#define TIMER_DISABLE                  0xFFC00644
#define TIMER_STATUS                   0xFFC00648
#define SIC_RVECT                      0xFFC00108 /* Interrupt Reset Vector Address Register */
#define SIC_IMASK                      0xFFC0010C /* Interrupt Mask Register */
#define SIC_IAR0                       0xFFC00110 /* Interrupt Assignment Register 0 */
#define SIC_IAR1                       0xFFC00114 /* Interrupt Assignment Register 1 */
#define SIC_IAR2                       0xFFC00118 /* Interrupt Assignment Register 2 */
#define SIC_IAR3                       0xFFC0011C /* Interrupt Assignment Register 3 */
#define SIC_ISR                        0xFFC00120 /* Interrupt Status Register */
#define SIC_IWR                        0xFFC00124 /* Interrupt Wakeup Register */
#define UART_THR                       0xFFC00400 /* Transmit Holding */
#define UART_DLL                       0xFFC00400 /* Divisor Latch Low Byte */
#define UART_DLH                       0xFFC00404 /* Divisor Latch High Byte */
#define UART_IER                       0xFFC00404
#define UART_IIR                       0xFFC00408
#define UART_LCR                       0xFFC0040C
#define UART_MCR                       0xFFC00410
#define UART_LSR                       0xFFC00414
#define UART_SCR                       0xFFC0041C
#define UART_RBR                       0xFFC00400 /* Receive Buffer */
#define UART_GCTL                      0xFFC00424
#define SPT0_TX_CONFIG0                0xFFC00800
#define SPT0_TX_CONFIG1                0xFFC00804
#define SPT0_RX_CONFIG0                0xFFC00820
#define SPT0_RX_CONFIG1                0xFFC00824
#define SPT0_TX                        0xFFC00810
#define SPT0_RX                        0xFFC00818
#define SPT0_TSCLKDIV                  0xFFC00808
#define SPT0_RSCLKDIV                  0xFFC00828
#define SPT0_TFSDIV                    0xFFC0080C
#define SPT0_RFSDIV                    0xFFC0082C
#define SPT0_STAT                      0xFFC00830
#define SPT0_MTCS0                     0xFFC00840
#define SPT0_MTCS1                     0xFFC00844
#define SPT0_MTCS2                     0xFFC00848
#define SPT0_MTCS3                     0xFFC0084C
#define SPT0_MRCS0                     0xFFC00850
#define SPT0_MRCS1                     0xFFC00854
#define SPT0_MRCS2                     0xFFC00858
#define SPT0_MRCS3                     0xFFC0085C
#define SPT0_MCMC1                     0xFFC00838
#define SPT0_MCMC2                     0xFFC0083C
#define SPT0_CHNL                      0xFFC00834
#define SPT1_TX_CONFIG0                0xFFC00900
#define SPT1_TX_CONFIG1                0xFFC00904
#define SPT1_RX_CONFIG0                0xFFC00920
#define SPT1_RX_CONFIG1                0xFFC00924
#define SPT1_TX                        0xFFC00910
#define SPT1_RX                        0xFFC00918
#define SPT1_TSCLKDIV                  0xFFC00908
#define SPT1_RSCLKDIV                  0xFFC00928
#define SPT1_TFSDIV                    0xFFC0090C
#define SPT1_RFSDIV                    0xFFC0092C
#define SPT1_STAT                      0xFFC00930
#define SPT1_MTCS0                     0xFFC00940
#define SPT1_MTCS1                     0xFFC00944
#define SPT1_MTCS2                     0xFFC00948
#define SPT1_MTCS3                     0xFFC0094C
#define SPT1_MRCS0                     0xFFC00950
#define SPT1_MRCS1                     0xFFC00954
#define SPT1_MRCS2                     0xFFC00958
#define SPT1_MRCS3                     0xFFC0095C
#define SPT1_MCMC1                     0xFFC00938
#define SPT1_MCMC2                     0xFFC0093C
#define SPT1_CHNL                      0xFFC00934
#define PPI_CONTROL                    0xFFC01000
#define PPI_STATUS                     0xFFC01004
#define PPI_DELAY                      0xFFC0100C
#define PPI_COUNT                      0xFFC01008
#define PPI_FRAME                      0xFFC01010
#define PLL_CTL                        0xFFC00000 /* PLL Control register (16-bit) */
#define PLL_DIV                        0xFFC00004 /* PLL Divide Register (16-bit) */
#define VR_CTL                         0xFFC00008 /* Voltage Regulator Control Register (16-bit) */
#define PLL_STAT                       0xFFC0000C /* PLL Status register (16-bit) */
#define PLL_LOCKCNT                    0xFFC00010 /* PLL Lock Count register (16-bit) */
#define SWRST                          0xFFC00100 /* Software Reset Register (16-bit) */
#define SYSCR                          0xFFC00104 /* System Configuration register */
#define EVT_OVERRIDE                   0xFFE02100
#define CHIPID                         0xFFC00014
#define TBUFCTL                        0xFFE06000 /* Trace Buffer Control Register */
#define TBUFSTAT                       0xFFE06004 /* Trace Buffer Status Register */
#define TBUF                           0xFFE06100 /* Trace Buffer */
#define PFCTL                          0xFFE08000
#define PFCNTR0                        0xFFE08100
#define PFCNTR1                        0xFFE08104
#define WDOG_CTL                       0xFFC00200 /* Watchdog Control Register */
#define WDOG_CNT                       0xFFC00204 /* Watchdog Count Register */
#define WDOG_STAT                      0xFFC00208 /* Watchdog Status Register */
#define RTC_STAT                       0xFFC00300
#define RTC_ICTL                       0xFFC00304
#define RTC_ISTAT                      0xFFC00308
#define RTC_SWCNT                      0xFFC0030C
#define RTC_ALARM                      0xFFC00310
#define RTC_PREN                       0xFFC00314
#define SPI_CTL                        0xFFC00500
#define SPI_FLG                        0xFFC00504
#define SPI_STAT                       0xFFC00508
#define SPI_TDBR                       0xFFC0050C
#define SPI_RDBR                       0xFFC00510
#define SPI_BAUD                       0xFFC00514
#define SPI_SHADOW                     0xFFC00518
#define FIO_FLAG_D                     0xFFC00700
#define FIO_FLAG_C                     0xFFC00704
#define FIO_FLAG_S                     0xFFC00708
#define FIO_FLAG_T                     0xFFC0070C
#define FIO_MASKA_D                    0xFFC00710
#define FIO_MASKA_C                    0xFFC00714
#define FIO_MASKA_S                    0xFFC00718
#define FIO_MASKA_T                    0xFFC0071C
#define FIO_MASKB_D                    0xFFC00720
#define FIO_MASKB_C                    0xFFC00724
#define FIO_MASKB_S                    0xFFC00728
#define FIO_MASKB_T                    0xFFC0072C
#define FIO_DIR                        0xFFC00730
#define FIO_POLAR                      0xFFC00734
#define FIO_EDGE                       0xFFC00738
#define FIO_BOTH                       0xFFC0073C
#define FIO_INEN                       0xFFC00740
#define SPORT0_TCR1                    0xFFC00800 /* SPORT0 Transmit Configuration 1 Register */
#define SPORT0_TCR2                    0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */
#define SPORT0_TCLKDIV                 0xFFC00808 /* SPORT0 Transmit Clock Divider */
#define SPORT0_TFSDIV                  0xFFC0080C /* SPORT0 Transmit Frame Sync Divider */
#define SPORT0_TX                      0xFFC00810 /* SPORT0 TX Data Register */
#define SPORT0_RX                      0xFFC00818 /* SPORT0 RX Data Register */
#define SPORT0_RCR1                    0xFFC00820 /* SPORT0 Transmit Configuration 1 Register */
#define SPORT0_RCR2                    0xFFC00824 /* SPORT0 Transmit Configuration 2 Register */
#define SPORT0_RCLKDIV                 0xFFC00828 /* SPORT0 Receive Clock Divider */
#define SPORT0_RFSDIV                  0xFFC0082C /* SPORT0 Receive Frame Sync Divider */
#define SPORT0_STAT                    0xFFC00830 /* SPORT0 Status Register */
#define SPORT0_CHNL                    0xFFC00834 /* SPORT0 Current Channel Register */
#define SPORT0_MCMC1                   0xFFC00838 /* SPORT0 Multi-Channel Configuration Register 1 */
#define SPORT0_MCMC2                   0xFFC0083C /* SPORT0 Multi-Channel Configuration Register 2 */
#define SPORT1_TCR1                    0xFFC00900 /* SPORT1 Transmit Configuration 1 Register */
#define SPORT1_TCR2                    0xFFC00904 /* SPORT1 Transmit Configuration 2 Register */