adsp-edn-extended_def.h

uboot200903最新版本的通用uboot

/* DO NOT EDIT THIS FILE
 * Automatically generated by generate-def-headers.xsl
 * DO NOT EDIT THIS FILE
 */

#ifndef __BFIN_DEF_ADSP_EDN_extended__
#define __BFIN_DEF_ADSP_EDN_extended__

#define ILAT                           0xFFE0210C /* Interrupt Latch Register */
#define IMASK                          0xFFE02104 /* Interrupt Mask Register */
#define IPEND                          0xFFE02108 /* Interrupt Pending Register */
#define IPRIO                          0xFFE02110 /* Interrupt Priority Register */
#define TCNTL                          0xFFE03000 /* Core Timer Control Register */
#define TPERIOD                        0xFFE03004 /* Core Timer Period Register */
#define TSCALE                         0xFFE03008 /* Core Timer Scale Register */
#define TCOUNT                         0xFFE0300C /* Core Timer Count Register */
#define SRAM_BASE_ADDR                 0xFFE00000 /* SRAM Base Address (Read Only) */
#define DMEM_CONTROL                   0xFFE00004 /* Data memory control */
#define DCPLB_FAULT_STATUS             0xFFE00008 /* L1 Data Memory Controller Register */
#define DCPLB_FAULT_ADDR               0xFFE0000C
#define DCPLB_ADDR0                    0xFFE00100 /* Data Cache Protection Lookaside Buffer 0 */
#define DCPLB_ADDR1                    0xFFE00104 /* Data Cache Protection Lookaside Buffer 1 */
#define DCPLB_ADDR2                    0xFFE00108 /* Data Cache Protection Lookaside Buffer 2 */
#define DCPLB_ADDR3                    0xFFE0010C /* Data Cache Protection Lookaside Buffer 3 */
#define DCPLB_ADDR4                    0xFFE00110 /* Data Cache Protection Lookaside Buffer 4 */
#define DCPLB_ADDR5                    0xFFE00114 /* Data Cache Protection Lookaside Buffer 5 */
#define DCPLB_ADDR6                    0xFFE00118 /* Data Cache Protection Lookaside Buffer 6 */
#define DCPLB_ADDR7                    0xFFE0011C /* Data Cache Protection Lookaside Buffer 7 */
#define DCPLB_ADDR8                    0xFFE00120 /* Data Cache Protection Lookaside Buffer 8 */
#define DCPLB_ADDR9                    0xFFE00124 /* Data Cache Protection Lookaside Buffer 9 */
#define DCPLB_ADDR10                   0xFFE00128 /* Data Cache Protection Lookaside Buffer 10 */
#define DCPLB_ADDR11                   0xFFE0012C /* Data Cache Protection Lookaside Buffer 11 */
#define DCPLB_ADDR12                   0xFFE00130 /* Data Cache Protection Lookaside Buffer 12 */
#define DCPLB_ADDR13                   0xFFE00134 /* Data Cache Protection Lookaside Buffer 13 */
#define DCPLB_ADDR14                   0xFFE00138 /* Data Cache Protection Lookaside Buffer 14 */
#define DCPLB_ADDR15                   0xFFE0013C /* Data Cache Protection Lookaside Buffer 15 */
#define DCPLB_DATA0                    0xFFE00200 /* Data Cache 0 Status */
#define DCPLB_DATA1                    0xFFE00204 /* Data Cache 1 Status */
#define DCPLB_DATA2                    0xFFE00208 /* Data Cache 2 Status */
#define DCPLB_DATA3                    0xFFE0020C /* Data Cache 3 Status */
#define DCPLB_DATA4                    0xFFE00210 /* Data Cache 4 Status */
#define DCPLB_DATA5                    0xFFE00214 /* Data Cache 5 Status */
#define DCPLB_DATA6                    0xFFE00218 /* Data Cache 6 Status */
#define DCPLB_DATA7                    0xFFE0021C /* Data Cache 7 Status */
#define DCPLB_DATA8                    0xFFE00220 /* Data Cache 8 Status */
#define DCPLB_DATA9                    0xFFE00224 /* Data Cache 9 Status */
#define DCPLB_DATA10                   0xFFE00228 /* Data Cache 10 Status */
#define DCPLB_DATA11                   0xFFE0022C /* Data Cache 11 Status */
#define DCPLB_DATA12                   0xFFE00230 /* Data Cache 12 Status */
#define DCPLB_DATA13                   0xFFE00234 /* Data Cache 13 Status */
#define DCPLB_DATA14                   0xFFE00238 /* Data Cache 14 Status */
#define DCPLB_DATA15                   0xFFE0023C /* Data Cache 15 Status */
#define DTEST_COMMAND                  0xFFE00300 /* Data Test Command Register */
#define DTEST_DATA0                    0xFFE00400 /* Data Test Data Register */
#define DTEST_DATA1                    0xFFE00404 /* Data Test Data Register */
#define EVT0                           0xFFE02000 /* Event Vector 0 ESR Address */
#define EVT1                           0xFFE02004 /* Event Vector 1 ESR Address */
#define EVT2                           0xFFE02008 /* Event Vector 2 ESR Address */
#define EVT3                           0xFFE0200C /* Event Vector 3 ESR Address */
#define EVT4                           0xFFE02010 /* Event Vector 4 ESR Address */
#define EVT5                           0xFFE02014 /* Event Vector 5 ESR Address */
#define EVT6                           0xFFE02018 /* Event Vector 6 ESR Address */
#define EVT7                           0xFFE0201C /* Event Vector 7 ESR Address */
#define EVT8                           0xFFE02020 /* Event Vector 8 ESR Address */
#define EVT9                           0xFFE02024 /* Event Vector 9 ESR Address */
#define EVT10                          0xFFE02028 /* Event Vector 10 ESR Address */
#define EVT11                          0xFFE0202C /* Event Vector 11 ESR Address */
#define EVT12                          0xFFE02030 /* Event Vector 12 ESR Address */
#define EVT13                          0xFFE02034 /* Event Vector 13 ESR Address */
#define EVT14                          0xFFE02038 /* Event Vector 14 ESR Address */
#define EVT15                          0xFFE0203C /* Event Vector 15 ESR Address */
#define IMEM_CONTROL                   0xFFE01004 /* Instruction Memory Control */
#define ICPLB_FAULT_STATUS             0xFFE01008
#define ICPLB_FAULT_ADDR               0xFFE0100C
#define ICPLB_ADDR0                    0xFFE01100 /* Instruction Cacheability Protection Lookaside Buffer 0 */
#define ICPLB_ADDR1                    0xFFE01104 /* Instruction Cacheability Protection Lookaside Buffer 1 */
#define ICPLB_ADDR2                    0xFFE01108 /* Instruction Cacheability Protection Lookaside Buffer 2 */
#define ICPLB_ADDR3                    0xFFE0110C /* Instruction Cacheability Protection Lookaside Buffer 3 */
#define ICPLB_ADDR4                    0xFFE01110 /* Instruction Cacheability Protection Lookaside Buffer 4 */
#define ICPLB_ADDR5                    0xFFE01114 /* Instruction Cacheability Protection Lookaside Buffer 5 */
#define ICPLB_ADDR6                    0xFFE01118 /* Instruction Cacheability Protection Lookaside Buffer 6 */
#define ICPLB_ADDR7                    0xFFE0111C /* Instruction Cacheability Protection Lookaside Buffer 7 */
#define ICPLB_ADDR8                    0xFFE01120 /* Instruction Cacheability Protection Lookaside Buffer 8 */
#define ICPLB_ADDR9                    0xFFE01124 /* Instruction Cacheability Protection Lookaside Buffer 9 */
#define ICPLB_ADDR10                   0xFFE01128 /* Instruction Cacheability Protection Lookaside Buffer 10 */
#define ICPLB_ADDR11                   0xFFE0112C /* Instruction Cacheability Protection Lookaside Buffer 11 */
#define ICPLB_ADDR12                   0xFFE01130 /* Instruction Cacheability Protection Lookaside Buffer 12 */
#define ICPLB_ADDR13                   0xFFE01134 /* Instruction Cacheability Protection Lookaside Buffer 13 */
#define ICPLB_ADDR14                   0xFFE01138 /* Instruction Cacheability Protection Lookaside Buffer 14 */
#define ICPLB_ADDR15                   0xFFE0113C /* Instruction Cacheability Protection Lookaside Buffer 15 */
#define ICPLB_DATA0                    0xFFE01200 /* Instruction Cache 0 Status */
#define ICPLB_DATA1                    0xFFE01204 /* Instruction Cache 1 Status */
#define ICPLB_DATA2                    0xFFE01208 /* Instruction Cache 2 Status */
#define ICPLB_DATA3                    0xFFE0120C /* Instruction Cache 3 Status */
#define ICPLB_DATA4                    0xFFE01210 /* Instruction Cache 4 Status */
#define ICPLB_DATA5                    0xFFE01214 /* Instruction Cache 5 Status */
#define ICPLB_DATA6                    0xFFE01218 /* Instruction Cache 6 Status */
#define ICPLB_DATA7                    0xFFE0121C /* Instruction Cache 7 Status */
#define ICPLB_DATA8                    0xFFE01220 /* Instruction Cache 8 Status */
#define ICPLB_DATA9                    0xFFE01224 /* Instruction Cache 9 Status */
#define ICPLB_DATA10                   0xFFE01228 /* Instruction Cache 10 Status */
#define ICPLB_DATA11                   0xFFE0122C /* Instruction Cache 11 Status */
#define ICPLB_DATA12                   0xFFE01230 /* Instruction Cache 12 Status */
#define ICPLB_DATA13                   0xFFE01234 /* Instruction Cache 13 Status */
#define ICPLB_DATA14                   0xFFE01238 /* Instruction Cache 14 Status */
#define ICPLB_DATA15                   0xFFE0123C /* Instruction Cache 15 Status */
#define ITEST_COMMAND                  0xFFE01300 /* Instruction Test Command Register */
#define ITEST_DATA0                    0xFFE01400 /* Instruction Test Data Register */
#define ITEST_DATA1                    0xFFE01404 /* Instruction Test Data Register */
#define MDMAFLX0_DMACNFG_D             0xFFC00E08
#define MDMAFLX0_XCOUNT_D              0xFFC00E10
#define MDMAFLX0_XMODIFY_D             0xFFC00E14
#define MDMAFLX0_YCOUNT_D              0xFFC00E18
#define MDMAFLX0_YMODIFY_D             0xFFC00E1C
#define MDMAFLX0_IRQSTAT_D             0xFFC00E28
#define MDMAFLX0_PMAP_D                0xFFC00E2C
#define MDMAFLX0_CURXCOUNT_D           0xFFC00E30
#define MDMAFLX0_CURYCOUNT_D           0xFFC00E38
#define MDMAFLX0_DMACNFG_S             0xFFC00E48
#define MDMAFLX0_XCOUNT_S              0xFFC00E50
#define MDMAFLX0_XMODIFY_S             0xFFC00E54
#define MDMAFLX0_YCOUNT_S              0xFFC00E58
#define MDMAFLX0_YMODIFY_S             0xFFC00E5C
#define MDMAFLX0_IRQSTAT_S             0xFFC00E68
#define MDMAFLX0_PMAP_S                0xFFC00E6C
#define MDMAFLX0_CURXCOUNT_S           0xFFC00E70
#define MDMAFLX0_CURYCOUNT_S           0xFFC00E78
#define MDMAFLX1_DMACNFG_D             0xFFC00E88
#define MDMAFLX1_XCOUNT_D              0xFFC00E90
#define MDMAFLX1_XMODIFY_D             0xFFC00E94
#define MDMAFLX1_YCOUNT_D              0xFFC00E98
#define MDMAFLX1_YMODIFY_D             0xFFC00E9C
#define MDMAFLX1_IRQSTAT_D             0xFFC00EA8
#define MDMAFLX1_PMAP_D                0xFFC00EAC
#define MDMAFLX1_CURXCOUNT_D           0xFFC00EB0
#define MDMAFLX1_CURYCOUNT_D           0xFFC00EB8
#define MDMAFLX1_DMACNFG_S             0xFFC00EC8
#define MDMAFLX1_XCOUNT_S              0xFFC00ED0
#define MDMAFLX1_XMODIFY_S             0xFFC00ED4
#define MDMAFLX1_YCOUNT_S              0xFFC00ED8
#define MDMAFLX1_YMODIFY_S             0xFFC00EDC
#define MDMAFLX1_IRQSTAT_S             0xFFC00EE8
#define MDMAFLX1_PMAP_S                0xFFC00EEC
#define MDMAFLX1_CURXCOUNT_S           0xFFC00EF0
#define MDMAFLX1_CURYCOUNT_S           0xFFC00EF8
#define DMAFLX0_DMACNFG                0xFFC00C08
#define DMAFLX0_XCOUNT                 0xFFC00C10
#define DMAFLX0_XMODIFY                0xFFC00C14
#define DMAFLX0_YCOUNT                 0xFFC00C18
#define DMAFLX0_YMODIFY                0xFFC00C1C
#define DMAFLX0_IRQSTAT                0xFFC00C28
#define DMAFLX0_PMAP                   0xFFC00C2C
#define DMAFLX0_CURXCOUNT              0xFFC00C30
#define DMAFLX0_CURYCOUNT              0xFFC00C38
#define DMAFLX1_DMACNFG                0xFFC00C48
#define DMAFLX1_XCOUNT                 0xFFC00C50
#define DMAFLX1_XMODIFY                0xFFC00C54
#define DMAFLX1_YCOUNT                 0xFFC00C58
#define DMAFLX1_YMODIFY                0xFFC00C5C
#define DMAFLX1_IRQSTAT                0xFFC00C68
#define DMAFLX1_PMAP                   0xFFC00C6C
#define DMAFLX1_CURXCOUNT              0xFFC00C70
#define DMAFLX1_CURYCOUNT              0xFFC00C78
#define DMAFLX2_DMACNFG                0xFFC00C88
#define DMAFLX2_XCOUNT                 0xFFC00C90
#define DMAFLX2_XMODIFY                0xFFC00C94
#define DMAFLX2_YCOUNT                 0xFFC00C98
#define DMAFLX2_YMODIFY                0xFFC00C9C
#define DMAFLX2_IRQSTAT                0xFFC00CA8
#define DMAFLX2_PMAP                   0xFFC00CAC
#define DMAFLX2_CURXCOUNT              0xFFC00CB0
#define DMAFLX2_CURYCOUNT              0xFFC00CB8
#define DMAFLX3_DMACNFG                0xFFC00CC8
#define DMAFLX3_XCOUNT                 0xFFC00CD0
#define DMAFLX3_XMODIFY                0xFFC00CD4
#define DMAFLX3_YCOUNT                 0xFFC00CD8
#define DMAFLX3_YMODIFY                0xFFC00CDC
#define DMAFLX3_IRQSTAT                0xFFC00CE8
#define DMAFLX3_PMAP                   0xFFC00CEC
#define DMAFLX3_CURXCOUNT              0xFFC00CF0
#define DMAFLX3_CURYCOUNT              0xFFC00CF8
#define DMAFLX4_DMACNFG                0xFFC00D08