adsp-edn-dual-core-extended_def.h

uboot200903最新版本的通用uboot

#define MDMA2_S0_X_MODIFY              0xFFC00F54
#define MDMA2_S0_Y_MODIFY              0xFFC00F5C
#define MDMA2_S0_CURR_DESC_PTR         0xFFC00F60
#define MDMA2_S0_CURR_ADDR             0xFFC00F64
#define MDMA2_S0_CURR_X_COUNT          0xFFC00F70
#define MDMA2_S0_CURR_Y_COUNT          0xFFC00F78
#define MDMA2_S0_IRQ_STATUS            0xFFC00F68
#define MDMA2_S0_PERIPHERAL_MAP        0xFFC00F6C
#define MDMA2_D0_CONFIG                0xFFC00F08
#define MDMA2_D0_NEXT_DESC_PTR         0xFFC00F00
#define MDMA2_D0_START_ADDR            0xFFC00F04
#define MDMA2_D0_X_COUNT               0xFFC00F10
#define MDMA2_D0_Y_COUNT               0xFFC00F18
#define MDMA2_D0_X_MODIFY              0xFFC00F14
#define MDMA2_D0_Y_MODIFY              0xFFC00F1C
#define MDMA2_D0_CURR_DESC_PTR         0xFFC00F20
#define MDMA2_D0_CURR_ADDR             0xFFC00F24
#define MDMA2_D0_CURR_X_COUNT          0xFFC00F30
#define MDMA2_D0_CURR_Y_COUNT          0xFFC00F38
#define MDMA2_D0_IRQ_STATUS            0xFFC00F28
#define MDMA2_D0_PERIPHERAL_MAP        0xFFC00F2C
#define MDMA2_S1_CONFIG                0xFFC00FC8
#define MDMA2_S1_NEXT_DESC_PTR         0xFFC00FC0
#define MDMA2_S1_START_ADDR            0xFFC00FC4
#define MDMA2_S1_X_COUNT               0xFFC00FD0
#define MDMA2_S1_Y_COUNT               0xFFC00FD8
#define MDMA2_S1_X_MODIFY              0xFFC00FD4
#define MDMA2_S1_Y_MODIFY              0xFFC00FDC
#define MDMA2_S1_CURR_DESC_PTR         0xFFC00FE0
#define MDMA2_S1_CURR_ADDR             0xFFC00FE4
#define MDMA2_S1_CURR_X_COUNT          0xFFC00FF0
#define MDMA2_S1_CURR_Y_COUNT          0xFFC00FF8
#define MDMA2_S1_IRQ_STATUS            0xFFC00FE8
#define MDMA2_S1_PERIPHERAL_MAP        0xFFC00FEC
#define MDMA2_D1_CONFIG                0xFFC00F88
#define MDMA2_D1_NEXT_DESC_PTR         0xFFC00F80
#define MDMA2_D1_START_ADDR            0xFFC00F84
#define MDMA2_D1_X_COUNT               0xFFC00F90
#define MDMA2_D1_Y_COUNT               0xFFC00F98
#define MDMA2_D1_X_MODIFY              0xFFC00F94
#define MDMA2_D1_Y_MODIFY              0xFFC00F9C
#define MDMA2_D1_CURR_DESC_PTR         0xFFC00FA0
#define MDMA2_D1_CURR_ADDR             0xFFC00FA4
#define MDMA2_D1_CURR_X_COUNT          0xFFC00FB0
#define MDMA2_D1_CURR_Y_COUNT          0xFFC00FB8
#define MDMA2_D1_IRQ_STATUS            0xFFC00FA8
#define MDMA2_D1_PERIPHERAL_MAP        0xFFC00FAC
#define TIMER0_CONFIG                  0xFFC00600
#define TIMER0_COUNTER                 0xFFC00604
#define TIMER0_PERIOD                  0xFFC00608
#define TIMER0_WIDTH                   0xFFC0060C
#define TIMER1_CONFIG                  0xFFC00610
#define TIMER1_COUNTER                 0xFFC00614
#define TIMER1_PERIOD                  0xFFC00618
#define TIMER1_WIDTH                   0xFFC0061C
#define TIMER2_CONFIG                  0xFFC00620
#define TIMER2_COUNTER                 0xFFC00624
#define TIMER2_PERIOD                  0xFFC00628
#define TIMER2_WIDTH                   0xFFC0062C
#define TIMER3_CONFIG                  0xFFC00630
#define TIMER3_COUNTER                 0xFFC00634
#define TIMER3_PERIOD                  0xFFC00638
#define TIMER3_WIDTH                   0xFFC0063C
#define TIMER4_CONFIG                  0xFFC00640
#define TIMER4_COUNTER                 0xFFC00644
#define TIMER4_PERIOD                  0xFFC00648
#define TIMER4_WIDTH                   0xFFC0064C
#define TIMER5_CONFIG                  0xFFC00650
#define TIMER5_COUNTER                 0xFFC00654
#define TIMER5_PERIOD                  0xFFC00658
#define TIMER5_WIDTH                   0xFFC0065C
#define TIMER6_CONFIG                  0xFFC00660
#define TIMER6_COUNTER                 0xFFC00664
#define TIMER6_PERIOD                  0xFFC00668
#define TIMER6_WIDTH                   0xFFC0066C
#define TIMER7_CONFIG                  0xFFC00670
#define TIMER7_COUNTER                 0xFFC00674
#define TIMER7_PERIOD                  0xFFC00678
#define TIMER7_WIDTH                   0xFFC0067C
#define TIMER8_CONFIG                  0xFFC01600
#define TIMER8_COUNTER                 0xFFC01604
#define TIMER8_PERIOD                  0xFFC01608
#define TIMER8_WIDTH                   0xFFC0160C
#define TIMER9_CONFIG                  0xFFC01610
#define TIMER9_COUNTER                 0xFFC01614
#define TIMER9_PERIOD                  0xFFC01618
#define TIMER9_WIDTH                   0xFFC0161C
#define TIMER10_CONFIG                 0xFFC01620
#define TIMER10_COUNTER                0xFFC01624
#define TIMER10_PERIOD                 0xFFC01628
#define TIMER10_WIDTH                  0xFFC0162C
#define TIMER11_CONFIG                 0xFFC01630
#define TIMER11_COUNTER                0xFFC01634
#define TIMER11_PERIOD                 0xFFC01638
#define TIMER11_WIDTH                  0xFFC0163C
#define TMRS4_ENABLE                   0xFFC01640
#define TMRS4_DISABLE                  0xFFC01644
#define TMRS4_STATUS                   0xFFC01648
#define TMRS8_ENABLE                   0xFFC00680
#define TMRS8_DISABLE                  0xFFC00684
#define TMRS8_STATUS                   0xFFC00688
#define FIO0_FLAG_D                    0xFFC00700
#define FIO0_FLAG_C                    0xFFC00704
#define FIO0_FLAG_S                    0xFFC00708
#define FIO0_FLAG_T                    0xFFC0070C
#define FIO0_MASKA_D                   0xFFC00710
#define FIO0_MASKA_C                   0xFFC00714
#define FIO0_MASKA_S                   0xFFC00718
#define FIO0_MASKA_T                   0xFFC0071C
#define FIO0_MASKB_D                   0xFFC00720
#define FIO0_MASKB_C                   0xFFC00724
#define FIO0_MASKB_S                   0xFFC00728
#define FIO0_MASKB_T                   0xFFC0072C
#define FIO0_DIR                       0xFFC00730
#define FIO0_POLAR                     0xFFC00734
#define FIO0_EDGE                      0xFFC00738
#define FIO0_BOTH                      0xFFC0073C
#define FIO0_INEN                      0xFFC00740
#define FIO1_FLAG_D                    0xFFC01500
#define FIO1_FLAG_C                    0xFFC01504
#define FIO1_FLAG_S                    0xFFC01508
#define FIO1_FLAG_T                    0xFFC0150C
#define FIO1_MASKA_D                   0xFFC01510
#define FIO1_MASKA_C                   0xFFC01514
#define FIO1_MASKA_S                   0xFFC01518
#define FIO1_MASKA_T                   0xFFC0151C
#define FIO1_MASKB_D                   0xFFC01520
#define FIO1_MASKB_C                   0xFFC01524
#define FIO1_MASKB_S                   0xFFC01528
#define FIO1_MASKB_T                   0xFFC0152C
#define FIO1_DIR                       0xFFC01530
#define FIO1_POLAR                     0xFFC01534
#define FIO1_EDGE                      0xFFC01538
#define FIO1_BOTH                      0xFFC0153C
#define FIO1_INEN                      0xFFC01540
#define FIO2_FLAG_D                    0xFFC01700
#define FIO2_FLAG_C                    0xFFC01704
#define FIO2_FLAG_S                    0xFFC01708
#define FIO2_FLAG_T                    0xFFC0170C
#define FIO2_MASKA_D                   0xFFC01710
#define FIO2_MASKA_C                   0xFFC01714
#define FIO2_MASKA_S                   0xFFC01718
#define FIO2_MASKA_T                   0xFFC0171C
#define FIO2_MASKB_D                   0xFFC01720
#define FIO2_MASKB_C                   0xFFC01724
#define FIO2_MASKB_S                   0xFFC01728
#define FIO2_MASKB_T                   0xFFC0172C
#define FIO2_DIR                       0xFFC01730
#define FIO2_POLAR                     0xFFC01734
#define FIO2_EDGE                      0xFFC01738
#define FIO2_BOTH                      0xFFC0173C
#define FIO2_INEN                      0xFFC01740
#define SPORT0_TCR1                    0xFFC00800
#define SPORT0_TCR2                    0xFFC00804
#define SPORT0_TCLKDIV                 0xFFC00808
#define SPORT0_TFSDIV                  0xFFC0080C
#define SPORT0_TX                      0xFFC00810
#define SPORT0_RX                      0xFFC00818
#define SPORT0_RCR1                    0xFFC00820
#define SPORT0_RCR2                    0xFFC00824
#define SPORT0_RCLKDIV                 0xFFC00828
#define SPORT0_RFSDIV                  0xFFC0082C
#define SPORT0_STAT                    0xFFC00830
#define SPORT0_CHNL                    0xFFC00834
#define SPORT0_MCMC1                   0xFFC00838
#define SPORT0_MCMC2                   0xFFC0083C
#define SPORT0_MTCS0                   0xFFC00840
#define SPORT0_MTCS1                   0xFFC00844
#define SPORT0_MTCS2                   0xFFC00848
#define SPORT0_MTCS3                   0xFFC0084C
#define SPORT0_MRCS0                   0xFFC00850
#define SPORT0_MRCS1                   0xFFC00854
#define SPORT0_MRCS2                   0xFFC00858
#define SPORT0_MRCS3                   0xFFC0085C
#define SPORT1_TCR1                    0xFFC00900
#define SPORT1_TCR2                    0xFFC00904
#define SPORT1_TCLKDIV                 0xFFC00908
#define SPORT1_TFSDIV                  0xFFC0090C
#define SPORT1_TX                      0xFFC00910
#define SPORT1_RX                      0xFFC00918
#define SPORT1_RCR1                    0xFFC00920
#define SPORT1_RCR2                    0xFFC00924
#define SPORT1_RCLKDIV                 0xFFC00928
#define SPORT1_RFSDIV                  0xFFC0092C
#define SPORT1_STAT                    0xFFC00930
#define SPORT1_CHNL                    0xFFC00934
#define SPORT1_MCMC1                   0xFFC00938
#define SPORT1_MCMC2                   0xFFC0093C
#define SPORT1_MTCS0                   0xFFC00940
#define SPORT1_MTCS1                   0xFFC00944
#define SPORT1_MTCS2                   0xFFC00948
#define SPORT1_MTCS3                   0xFFC0094C
#define SPORT1_MRCS0                   0xFFC00950
#define SPORT1_MRCS1                   0xFFC00954
#define SPORT1_MRCS2                   0xFFC00958
#define SPORT1_MRCS3                   0xFFC0095C
#define EVT0                           0xFFE02000
#define EVT1                           0xFFE02004
#define EVT2                           0xFFE02008
#define EVT3                           0xFFE0200C
#define EVT4                           0xFFE02010
#define EVT5                           0xFFE02014
#define EVT6                           0xFFE02018
#define EVT7                           0xFFE0201C
#define EVT8                           0xFFE02020
#define EVT9                           0xFFE02024
#define EVT10                          0xFFE02028
#define EVT11                          0xFFE0202C
#define EVT12                          0xFFE02030
#define EVT13                          0xFFE02034
#define EVT14                          0xFFE02038
#define EVT15                          0xFFE0203C
#define ILAT                           0xFFE0210C /* Interrupt Latch Register */
#define IMASK                          0xFFE02104 /* Interrupt Mask Register */
#define IPEND                          0xFFE02108 /* Interrupt Pending Register */
#define IPRIO                          0xFFE02110 /* Interrupt Priority Register */
#define TCNTL                          0xFFE03000
#define TPERIOD                        0xFFE03004
#define TSCALE                         0xFFE03008
#define TCOUNT                         0xFFE0300C

#endif /* __BFIN_DEF_ADSP_EDN_DUAL_CORE_extended__ */