adsp-edn-bf52x-extended_cdef.h

uboot200903最新版本的通用uboot

#define bfin_read_SPORT0_RCR1()        bfin_read16(SPORT0_RCR1)
#define bfin_write_SPORT0_RCR1(val)    bfin_write16(SPORT0_RCR1, val)
#define pSPORT0_RCR2                   ((uint16_t volatile *)SPORT0_RCR2) /* SPORT0 Transmit Configuration 2 Register */
#define bfin_read_SPORT0_RCR2()        bfin_read16(SPORT0_RCR2)
#define bfin_write_SPORT0_RCR2(val)    bfin_write16(SPORT0_RCR2, val)
#define pSPORT0_RCLKDIV                ((uint16_t volatile *)SPORT0_RCLKDIV) /* SPORT0 Receive Clock Divider */
#define bfin_read_SPORT0_RCLKDIV()     bfin_read16(SPORT0_RCLKDIV)
#define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV, val)
#define pSPORT0_RFSDIV                 ((uint16_t volatile *)SPORT0_RFSDIV) /* SPORT0 Receive Frame Sync Divider */
#define bfin_read_SPORT0_RFSDIV()      bfin_read16(SPORT0_RFSDIV)
#define bfin_write_SPORT0_RFSDIV(val)  bfin_write16(SPORT0_RFSDIV, val)
#define pSPORT0_STAT                   ((uint16_t volatile *)SPORT0_STAT) /* SPORT0 Status Register */
#define bfin_read_SPORT0_STAT()        bfin_read16(SPORT0_STAT)
#define bfin_write_SPORT0_STAT(val)    bfin_write16(SPORT0_STAT, val)
#define pSPORT0_CHNL                   ((uint16_t volatile *)SPORT0_CHNL) /* SPORT0 Current Channel Register */
#define bfin_read_SPORT0_CHNL()        bfin_read16(SPORT0_CHNL)
#define bfin_write_SPORT0_CHNL(val)    bfin_write16(SPORT0_CHNL, val)
#define pSPORT0_MCMC1                  ((uint16_t volatile *)SPORT0_MCMC1) /* SPORT0 Multi-Channel Configuration Register 1 */
#define bfin_read_SPORT0_MCMC1()       bfin_read16(SPORT0_MCMC1)
#define bfin_write_SPORT0_MCMC1(val)   bfin_write16(SPORT0_MCMC1, val)
#define pSPORT0_MCMC2                  ((uint16_t volatile *)SPORT0_MCMC2) /* SPORT0 Multi-Channel Configuration Register 2 */
#define bfin_read_SPORT0_MCMC2()       bfin_read16(SPORT0_MCMC2)
#define bfin_write_SPORT0_MCMC2(val)   bfin_write16(SPORT0_MCMC2, val)
#define pSPORT0_MTCS0                  ((uint32_t volatile *)SPORT0_MTCS0) /* SPORT0 Multi-Channel Transmit Select Register 0 */
#define bfin_read_SPORT0_MTCS0()       bfin_read32(SPORT0_MTCS0)
#define bfin_write_SPORT0_MTCS0(val)   bfin_write32(SPORT0_MTCS0, val)
#define pSPORT0_MTCS1                  ((uint32_t volatile *)SPORT0_MTCS1) /* SPORT0 Multi-Channel Transmit Select Register 1 */
#define bfin_read_SPORT0_MTCS1()       bfin_read32(SPORT0_MTCS1)
#define bfin_write_SPORT0_MTCS1(val)   bfin_write32(SPORT0_MTCS1, val)
#define pSPORT0_MTCS2                  ((uint32_t volatile *)SPORT0_MTCS2) /* SPORT0 Multi-Channel Transmit Select Register 2 */
#define bfin_read_SPORT0_MTCS2()       bfin_read32(SPORT0_MTCS2)
#define bfin_write_SPORT0_MTCS2(val)   bfin_write32(SPORT0_MTCS2, val)
#define pSPORT0_MTCS3                  ((uint32_t volatile *)SPORT0_MTCS3) /* SPORT0 Multi-Channel Transmit Select Register 3 */
#define bfin_read_SPORT0_MTCS3()       bfin_read32(SPORT0_MTCS3)
#define bfin_write_SPORT0_MTCS3(val)   bfin_write32(SPORT0_MTCS3, val)
#define pSPORT0_MRCS0                  ((uint32_t volatile *)SPORT0_MRCS0) /* SPORT0 Multi-Channel Receive Select Register 0 */
#define bfin_read_SPORT0_MRCS0()       bfin_read32(SPORT0_MRCS0)
#define bfin_write_SPORT0_MRCS0(val)   bfin_write32(SPORT0_MRCS0, val)
#define pSPORT0_MRCS1                  ((uint32_t volatile *)SPORT0_MRCS1) /* SPORT0 Multi-Channel Receive Select Register 1 */
#define bfin_read_SPORT0_MRCS1()       bfin_read32(SPORT0_MRCS1)
#define bfin_write_SPORT0_MRCS1(val)   bfin_write32(SPORT0_MRCS1, val)
#define pSPORT0_MRCS2                  ((uint32_t volatile *)SPORT0_MRCS2) /* SPORT0 Multi-Channel Receive Select Register 2 */
#define bfin_read_SPORT0_MRCS2()       bfin_read32(SPORT0_MRCS2)
#define bfin_write_SPORT0_MRCS2(val)   bfin_write32(SPORT0_MRCS2, val)
#define pSPORT0_MRCS3                  ((uint32_t volatile *)SPORT0_MRCS3) /* SPORT0 Multi-Channel Receive Select Register 3 */
#define bfin_read_SPORT0_MRCS3()       bfin_read32(SPORT0_MRCS3)
#define bfin_write_SPORT0_MRCS3(val)   bfin_write32(SPORT0_MRCS3, val)
#define pSPORT1_TCR1                   ((uint16_t volatile *)SPORT1_TCR1) /* SPORT1 Transmit Configuration 1 Register */
#define bfin_read_SPORT1_TCR1()        bfin_read16(SPORT1_TCR1)
#define bfin_write_SPORT1_TCR1(val)    bfin_write16(SPORT1_TCR1, val)
#define pSPORT1_TCR2                   ((uint16_t volatile *)SPORT1_TCR2) /* SPORT1 Transmit Configuration 2 Register */
#define bfin_read_SPORT1_TCR2()        bfin_read16(SPORT1_TCR2)
#define bfin_write_SPORT1_TCR2(val)    bfin_write16(SPORT1_TCR2, val)
#define pSPORT1_TCLKDIV                ((uint16_t volatile *)SPORT1_TCLKDIV) /* SPORT1 Transmit Clock Divider */
#define bfin_read_SPORT1_TCLKDIV()     bfin_read16(SPORT1_TCLKDIV)
#define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV, val)
#define pSPORT1_TFSDIV                 ((uint16_t volatile *)SPORT1_TFSDIV) /* SPORT1 Transmit Frame Sync Divider */
#define bfin_read_SPORT1_TFSDIV()      bfin_read16(SPORT1_TFSDIV)
#define bfin_write_SPORT1_TFSDIV(val)  bfin_write16(SPORT1_TFSDIV, val)
#define pSPORT1_TX                     ((uint32_t volatile *)SPORT1_TX) /* SPORT1 TX Data Register */
#define bfin_read_SPORT1_TX()          bfin_read32(SPORT1_TX)
#define bfin_write_SPORT1_TX(val)      bfin_write32(SPORT1_TX, val)
#define pSPORT1_RX                     ((uint32_t volatile *)SPORT1_RX) /* SPORT1 RX Data Register */
#define bfin_read_SPORT1_RX()          bfin_read32(SPORT1_RX)
#define bfin_write_SPORT1_RX(val)      bfin_write32(SPORT1_RX, val)
#define pSPORT1_RCR1                   ((uint16_t volatile *)SPORT1_RCR1) /* SPORT1 Transmit Configuration 1 Register */
#define bfin_read_SPORT1_RCR1()        bfin_read16(SPORT1_RCR1)
#define bfin_write_SPORT1_RCR1(val)    bfin_write16(SPORT1_RCR1, val)
#define pSPORT1_RCR2                   ((uint16_t volatile *)SPORT1_RCR2) /* SPORT1 Transmit Configuration 2 Register */
#define bfin_read_SPORT1_RCR2()        bfin_read16(SPORT1_RCR2)
#define bfin_write_SPORT1_RCR2(val)    bfin_write16(SPORT1_RCR2, val)
#define pSPORT1_RCLKDIV                ((uint16_t volatile *)SPORT1_RCLKDIV) /* SPORT1 Receive Clock Divider */
#define bfin_read_SPORT1_RCLKDIV()     bfin_read16(SPORT1_RCLKDIV)
#define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV, val)
#define pSPORT1_RFSDIV                 ((uint16_t volatile *)SPORT1_RFSDIV) /* SPORT1 Receive Frame Sync Divider */
#define bfin_read_SPORT1_RFSDIV()      bfin_read16(SPORT1_RFSDIV)
#define bfin_write_SPORT1_RFSDIV(val)  bfin_write16(SPORT1_RFSDIV, val)
#define pSPORT1_STAT                   ((uint16_t volatile *)SPORT1_STAT) /* SPORT1 Status Register */
#define bfin_read_SPORT1_STAT()        bfin_read16(SPORT1_STAT)
#define bfin_write_SPORT1_STAT(val)    bfin_write16(SPORT1_STAT, val)
#define pSPORT1_CHNL                   ((uint16_t volatile *)SPORT1_CHNL) /* SPORT1 Current Channel Register */
#define bfin_read_SPORT1_CHNL()        bfin_read16(SPORT1_CHNL)
#define bfin_write_SPORT1_CHNL(val)    bfin_write16(SPORT1_CHNL, val)
#define pSPORT1_MCMC1                  ((uint16_t volatile *)SPORT1_MCMC1) /* SPORT1 Multi-Channel Configuration Register 1 */
#define bfin_read_SPORT1_MCMC1()       bfin_read16(SPORT1_MCMC1)
#define bfin_write_SPORT1_MCMC1(val)   bfin_write16(SPORT1_MCMC1, val)
#define pSPORT1_MCMC2                  ((uint16_t volatile *)SPORT1_MCMC2) /* SPORT1 Multi-Channel Configuration Register 2 */
#define bfin_read_SPORT1_MCMC2()       bfin_read16(SPORT1_MCMC2)
#define bfin_write_SPORT1_MCMC2(val)   bfin_write16(SPORT1_MCMC2, val)
#define pSPORT1_MTCS0                  ((uint32_t volatile *)SPORT1_MTCS0) /* SPORT1 Multi-Channel Transmit Select Register 0 */
#define bfin_read_SPORT1_MTCS0()       bfin_read32(SPORT1_MTCS0)
#define bfin_write_SPORT1_MTCS0(val)   bfin_write32(SPORT1_MTCS0, val)
#define pSPORT1_MTCS1                  ((uint32_t volatile *)SPORT1_MTCS1) /* SPORT1 Multi-Channel Transmit Select Register 1 */
#define bfin_read_SPORT1_MTCS1()       bfin_read32(SPORT1_MTCS1)
#define bfin_write_SPORT1_MTCS1(val)   bfin_write32(SPORT1_MTCS1, val)
#define pSPORT1_MTCS2                  ((uint32_t volatile *)SPORT1_MTCS2) /* SPORT1 Multi-Channel Transmit Select Register 2 */
#define bfin_read_SPORT1_MTCS2()       bfin_read32(SPORT1_MTCS2)
#define bfin_write_SPORT1_MTCS2(val)   bfin_write32(SPORT1_MTCS2, val)
#define pSPORT1_MTCS3                  ((uint32_t volatile *)SPORT1_MTCS3) /* SPORT1 Multi-Channel Transmit Select Register 3 */
#define bfin_read_SPORT1_MTCS3()       bfin_read32(SPORT1_MTCS3)
#define bfin_write_SPORT1_MTCS3(val)   bfin_write32(SPORT1_MTCS3, val)
#define pSPORT1_MRCS0                  ((uint32_t volatile *)SPORT1_MRCS0) /* SPORT1 Multi-Channel Receive Select Register 0 */
#define bfin_read_SPORT1_MRCS0()       bfin_read32(SPORT1_MRCS0)
#define bfin_write_SPORT1_MRCS0(val)   bfin_write32(SPORT1_MRCS0, val)
#define pSPORT1_MRCS1                  ((uint32_t volatile *)SPORT1_MRCS1) /* SPORT1 Multi-Channel Receive Select Register 1 */
#define bfin_read_SPORT1_MRCS1()       bfin_read32(SPORT1_MRCS1)
#define bfin_write_SPORT1_MRCS1(val)   bfin_write32(SPORT1_MRCS1, val)
#define pSPORT1_MRCS2                  ((uint32_t volatile *)SPORT1_MRCS2) /* SPORT1 Multi-Channel Receive Select Register 2 */
#define bfin_read_SPORT1_MRCS2()       bfin_read32(SPORT1_MRCS2)
#define bfin_write_SPORT1_MRCS2(val)   bfin_write32(SPORT1_MRCS2, val)
#define pSPORT1_MRCS3                  ((uint32_t volatile *)SPORT1_MRCS3) /* SPORT1 Multi-Channel Receive Select Register 3 */
#define bfin_read_SPORT1_MRCS3()       bfin_read32(SPORT1_MRCS3)
#define bfin_write_SPORT1_MRCS3(val)   bfin_write32(SPORT1_MRCS3, val)
#define pEBIU_AMGCTL                   ((uint16_t volatile *)EBIU_AMGCTL) /* Asynchronous Memory Global Control Register */
#define bfin_read_EBIU_AMGCTL()        bfin_read16(EBIU_AMGCTL)
#define bfin_write_EBIU_AMGCTL(val)    bfin_write16(EBIU_AMGCTL, val)
#define pEBIU_AMBCTL0                  ((uint32_t volatile *)EBIU_AMBCTL0) /* Asynchronous Memory Bank Control Register 0 */
#define bfin_read_EBIU_AMBCTL0()       bfin_read32(EBIU_AMBCTL0)
#define bfin_write_EBIU_AMBCTL0(val)   bfin_write32(EBIU_AMBCTL0, val)
#define pEBIU_AMBCTL1                  ((uint32_t volatile *)EBIU_AMBCTL1) /* Asynchronous Memory Bank Control Register 1 */
#define bfin_read_EBIU_AMBCTL1()       bfin_read32(EBIU_AMBCTL1)
#define bfin_write_EBIU_AMBCTL1(val)   bfin_write32(EBIU_AMBCTL1, val)
#define pEBIU_SDGCTL                   ((uint32_t volatile *)EBIU_SDGCTL) /* SDRAM Global Control Register */
#define bfin_read_EBIU_SDGCTL()        bfin_read32(EBIU_SDGCTL)
#define bfin_write_EBIU_SDGCTL(val)    bfin_write32(EBIU_SDGCTL, val)
#define pEBIU_SDBCTL                   ((uint16_t volatile *)EBIU_SDBCTL) /* SDRAM Bank Control Register */
#define bfin_read_EBIU_SDBCTL()        bfin_read16(EBIU_SDBCTL)
#define bfin_write_EBIU_SDBCTL(val)    bfin_write16(EBIU_SDBCTL, val)
#define pEBIU_SDRRC                    ((uint16_t volatile *)EBIU_SDRRC) /* SDRAM Refresh Rate Control Register */
#define bfin_read_EBIU_SDRRC()         bfin_read16(EBIU_SDRRC)
#define bfin_write_EBIU_SDRRC(val)     bfin_write16(EBIU_SDRRC, val)
#define pEBIU_SDSTAT                   ((uint16_t volatile *)EBIU_SDSTAT) /* SDRAM Status Register */
#define bfin_read_EBIU_SDSTAT()        bfin_read16(EBIU_SDSTAT)
#define bfin_write_EBIU_SDSTAT(val)    bfin_write16(EBIU_SDSTAT, val)
#define pDMA0_NEXT_DESC_PTR            ((void * volatile *)DMA0_NEXT_DESC_PTR) /* DMA Channel 0 Next Descriptor Pointer Register */
#define bfin_read_DMA0_NEXT_DESC_PTR() bfin_readPTR(DMA0_NEXT_DESC_PTR)
#define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_writePTR(DMA0_NEXT_DESC_PTR, val)
#define pDMA0_START_ADDR               ((void * volatile *)DMA0_START_ADDR) /* DMA Channel 0 Start Address Register */
#define bfin_read_DMA0_START_ADDR()    bfin_readPTR(DMA0_START_ADDR)
#define bfin_write_DMA0_START_ADDR(val) bfin_writePTR(DMA0_START_ADDR, val)
#define pDMA0_CONFIG                   ((uint16_t volatile *)DMA0_CONFIG) /* DMA Channel 0 Configuration Register */
#define bfin_read_DMA0_CONFIG()        bfin_read16(DMA0_CONFIG)
#define bfin_write_DMA0_CONFIG(val)    bfin_write16(DMA0_CONFIG, val)
#define pDMA0_X_COUNT                  ((uint16_t volatile *)DMA0_X_COUNT) /* DMA Channel 0 X Count Register */
#define bfin_read_DMA0_X_COUNT()       bfin_read16(DMA0_X_COUNT)
#define bfin_write_DMA0_X_COUNT(val)   bfin_write16(DMA0_X_COUNT, val)
#define pDMA0_X_MODIFY                 ((uint16_t volatile *)DMA0_X_MODIFY) /* DMA Channel 0 X Modify Register */
#define bfin_read_DMA0_X_MODIFY()      bfin_read16(DMA0_X_MODIFY)
#define bfin_write_DMA0_X_MODIFY(val)  bfin_write16(DMA0_X_MODIFY, val)
#define pDMA0_Y_COUNT                  ((uint16_t volatile *)DMA0_Y_COUNT) /* DMA Channel 0 Y Count Register */
#define bfin_read_DMA0_Y_COUNT()       bfin_read16(DMA0_Y_COUNT)
#define bfin_write_DMA0_Y_COUNT(val)   bfin_write16(DMA0_Y_COUNT, val)
#define pDMA0_Y_MODIFY                 ((uint16_t volatile *)DMA0_Y_MODIFY) /* DMA Channel 0 Y Modify Register */
#define bfin_read_DMA0_Y_MODIFY()      bfin_read16(DMA0_Y_MODIFY)
#define bfin_write_DMA0_Y_MODIFY(val)  bfin_write16(DMA0_Y_MODIFY, val)
#define pDMA0_CURR_DESC_PTR            ((void * volatile *)DMA0_CURR_DESC_PTR) /* DMA Channel 0 Current Descriptor Pointer Register */