📄 imx-regs.h
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#ifndef _IMX_REGS_H#define _IMX_REGS_H/* ------------------------------------------------------------------------ * Motorola IMX system registers * ------------------------------------------------------------------------ * */#define IO_ADDRESS(x) ((x) | IMX_IO_BASE)# ifndef __ASSEMBLY__# define __REG(x) (*((volatile u32 *)IO_ADDRESS(x)))# define __REG2(x,y) (*(volatile u32 *)((u32)&__REG(x) + (y)))# else# define __REG(x) (x)# define __REG2(x,y) ((x)+(y))#endif#define IMX_IO_BASE 0x00200000/* * Register BASEs, based on OFFSETs * */#define IMX_AIPI1_BASE (0x00000 + IMX_IO_BASE)#define IMX_WDT_BASE (0x01000 + IMX_IO_BASE)#define IMX_TIM1_BASE (0x02000 + IMX_IO_BASE)#define IMX_TIM2_BASE (0x03000 + IMX_IO_BASE)#define IMX_RTC_BASE (0x04000 + IMX_IO_BASE)#define IMX_LCDC_BASE (0x05000 + IMX_IO_BASE)#define IMX_UART1_BASE (0x06000 + IMX_IO_BASE)#define IMX_UART2_BASE (0x07000 + IMX_IO_BASE)#define IMX_PWM_BASE (0x08000 + IMX_IO_BASE)#define IMX_DMAC_BASE (0x09000 + IMX_IO_BASE)#define IMX_AIPI2_BASE (0x10000 + IMX_IO_BASE)#define IMX_SIM_BASE (0x11000 + IMX_IO_BASE)#define IMX_USBD_BASE (0x12000 + IMX_IO_BASE)#define IMX_SPI1_BASE (0x13000 + IMX_IO_BASE)#define IMX_MMC_BASE (0x14000 + IMX_IO_BASE)#define IMX_ASP_BASE (0x15000 + IMX_IO_BASE)#define IMX_BTA_BASE (0x16000 + IMX_IO_BASE)#define IMX_I2C_BASE (0x17000 + IMX_IO_BASE)#define IMX_SSI_BASE (0x18000 + IMX_IO_BASE)#define IMX_SPI2_BASE (0x19000 + IMX_IO_BASE)#define IMX_MSHC_BASE (0x1A000 + IMX_IO_BASE)#define IMX_PLL_BASE (0x1B000 + IMX_IO_BASE)#define IMX_SYSCTRL_BASE (0x1B800 + IMX_IO_BASE)#define IMX_GPIO_BASE (0x1C000 + IMX_IO_BASE)#define IMX_EIM_BASE (0x20000 + IMX_IO_BASE)#define IMX_SDRAMC_BASE (0x21000 + IMX_IO_BASE)#define IMX_MMA_BASE (0x22000 + IMX_IO_BASE)#define IMX_AITC_BASE (0x23000 + IMX_IO_BASE)#define IMX_CSI_BASE (0x24000 + IMX_IO_BASE)/* Watchdog Registers*/#define WCR __REG(IMX_WDT_BASE + 0x00) /* Watchdog Control Register */#define WSR __REG(IMX_WDT_BASE + 0x04) /* Watchdog Service Register */#define WSTR __REG(IMX_WDT_BASE + 0x08) /* Watchdog Status Register *//* SYSCTRL Registers */#define SIDR __REG(IMX_SYSCTRL_BASE + 0x4) /* Silicon ID Register */#define FMCR __REG(IMX_SYSCTRL_BASE + 0x8) /* Function Multiplex Control Register */#define GPCR __REG(IMX_SYSCTRL_BASE + 0xC) /* Function Multiplex Control Register *//* Chip Select Registers */#define CS0U __REG(IMX_EIM_BASE) /* Chip Select 0 Upper Register */#define CS0L __REG(IMX_EIM_BASE + 0x4) /* Chip Select 0 Lower Register */#define CS1U __REG(IMX_EIM_BASE + 0x8) /* Chip Select 1 Upper Register */#define CS1L __REG(IMX_EIM_BASE + 0xc) /* Chip Select 1 Lower Register */#define CS2U __REG(IMX_EIM_BASE + 0x10) /* Chip Select 2 Upper Register */#define CS2L __REG(IMX_EIM_BASE + 0x14) /* Chip Select 2 Lower Register */#define CS3U __REG(IMX_EIM_BASE + 0x18) /* Chip Select 3 Upper Register */#define CS3L __REG(IMX_EIM_BASE + 0x1c) /* Chip Select 3 Lower Register */#define CS4U __REG(IMX_EIM_BASE + 0x20) /* Chip Select 4 Upper Register */#define CS4L __REG(IMX_EIM_BASE + 0x24) /* Chip Select 4 Lower Register */#define CS5U __REG(IMX_EIM_BASE + 0x28) /* Chip Select 5 Upper Register */#define CS5L __REG(IMX_EIM_BASE + 0x2c) /* Chip Select 5 Lower Register */#define EIM __REG(IMX_EIM_BASE + 0x30) /* EIM Configuration Register *//* SDRAM controller registers */#define SDCTL0 __REG(IMX_SDRAMC_BASE) /* SDRAM 0 Control Register */#define SDCTL1 __REG(IMX_SDRAMC_BASE + 0x4) /* SDRAM 1 Control Register */#define SDMISC __REG(IMX_SDRAMC_BASE + 0x14) /* Miscellaneous Register */#define SDRST __REG(IMX_SDRAMC_BASE + 0x18) /* SDRAM Reset Register *//* PLL registers */#define CSCR __REG(IMX_PLL_BASE) /* Clock Source Control Register */#define CSCR_SPLL_RESTART (1<<22)#define CSCR_MPLL_RESTART (1<<21)#define CSCR_SYSTEM_SEL (1<<16)#define CSCR_BCLK_DIV (0xf<<10)#define CSCR_MPU_PRESC (1<<15)#define CSCR_SPEN (1<<1)#define CSCR_MPEN (1<<0)#define MPCTL0 __REG(IMX_PLL_BASE + 0x4) /* MCU PLL Control Register 0 */#define MPCTL1 __REG(IMX_PLL_BASE + 0x8) /* MCU PLL and System Clock Register 1 */#define SPCTL0 __REG(IMX_PLL_BASE + 0xc) /* System PLL Control Register 0 */#define SPCTL1 __REG(IMX_PLL_BASE + 0x10) /* System PLL Control Register 1 */#define PCDR __REG(IMX_PLL_BASE + 0x20) /* Peripheral Clock Divider Register *//* * GPIO Module and I/O Multiplexer * x = 0..3 for reg_A, reg_B, reg_C, reg_D */#define DDIR(x) __REG2(IMX_GPIO_BASE + 0x00, ((x) & 3) << 8)#define OCR1(x) __REG2(IMX_GPIO_BASE + 0x04, ((x) & 3) << 8)#define OCR2(x) __REG2(IMX_GPIO_BASE + 0x08, ((x) & 3) << 8)#define ICONFA1(x) __REG2(IMX_GPIO_BASE + 0x0c, ((x) & 3) << 8)#define ICONFA2(x) __REG2(IMX_GPIO_BASE + 0x10, ((x) & 3) << 8)#define ICONFB1(x) __REG2(IMX_GPIO_BASE + 0x14, ((x) & 3) << 8)#define ICONFB2(x) __REG2(IMX_GPIO_BASE + 0x18, ((x) & 3) << 8)#define DR(x) __REG2(IMX_GPIO_BASE + 0x1c, ((x) & 3) << 8)#define GIUS(x) __REG2(IMX_GPIO_BASE + 0x20, ((x) & 3) << 8)#define SSR(x) __REG2(IMX_GPIO_BASE + 0x24, ((x) & 3) << 8)#define ICR1(x) __REG2(IMX_GPIO_BASE + 0x28, ((x) & 3) << 8)#define ICR2(x) __REG2(IMX_GPIO_BASE + 0x2c, ((x) & 3) << 8)#define IMR(x) __REG2(IMX_GPIO_BASE + 0x30, ((x) & 3) << 8)#define ISR(x) __REG2(IMX_GPIO_BASE + 0x34, ((x) & 3) << 8)#define GPR(x) __REG2(IMX_GPIO_BASE + 0x38, ((x) & 3) << 8)#define SWR(x) __REG2(IMX_GPIO_BASE + 0x3c, ((x) & 3) << 8)#define PUEN(x) __REG2(IMX_GPIO_BASE + 0x40, ((x) & 3) << 8)#define GPIO_PORT_MAX 3#define GPIO_PIN_MASK 0x1f#define GPIO_PORT_MASK (0x3 << 5)#define GPIO_PORT_SHIFT 5#define GPIO_PORTA (0<<5)#define GPIO_PORTB (1<<5)#define GPIO_PORTC (2<<5)#define GPIO_PORTD (3<<5)#define GPIO_OUT (1<<7)#define GPIO_IN (0<<7)#define GPIO_PUEN (1<<8)#define GPIO_PF (0<<9)#define GPIO_AF (1<<9)#define GPIO_OCR_SHIFT 10#define GPIO_OCR_MASK (3<<10)#define GPIO_AIN (0<<10)#define GPIO_BIN (1<<10)#define GPIO_CIN (2<<10)#define GPIO_DR (3<<10)#define GPIO_AOUT_SHIFT 12#define GPIO_AOUT_MASK (3<<12)#define GPIO_AOUT (0<<12)#define GPIO_AOUT_ISR (1<<12)#define GPIO_AOUT_0 (2<<12)#define GPIO_AOUT_1 (3<<12)#define GPIO_BOUT_SHIFT 14#define GPIO_BOUT_MASK (3<<14)#define GPIO_BOUT (0<<14)#define GPIO_BOUT_ISR (1<<14)#define GPIO_BOUT_0 (2<<14)#define GPIO_BOUT_1 (3<<14)#define GPIO_GIUS (1<<16)/* assignements for GPIO alternate/primary functions *//* FIXME: This list is not completed. The correct directions are * missing on some (many) pins */#define PA0_AIN_SPI2_CLK ( GPIO_GIUS | GPIO_PORTA | GPIO_OUT | 0 )#define PA0_AF_ETMTRACESYNC ( GPIO_PORTA | GPIO_AF | 0 )#define PA1_AOUT_SPI2_RXD ( GPIO_GIUS | GPIO_PORTA | GPIO_IN | 1 )#define PA1_PF_TIN ( GPIO_PORTA | GPIO_PF | 1 )#define PA2_PF_PWM0 ( GPIO_PORTA | GPIO_OUT | GPIO_PF | 2 )#define PA3_PF_CSI_MCLK ( GPIO_PORTA | GPIO_PF | 3 )#define PA4_PF_CSI_D0 ( GPIO_PORTA | GPIO_PF | 4 )#define PA5_PF_CSI_D1 ( GPIO_PORTA | GPIO_PF | 5 )#define PA6_PF_CSI_D2 ( GPIO_PORTA | GPIO_PF | 6 )#define PA7_PF_CSI_D3 ( GPIO_PORTA | GPIO_PF | 7 )#define PA8_PF_CSI_D4 ( GPIO_PORTA | GPIO_PF | 8 )#define PA9_PF_CSI_D5 ( GPIO_PORTA | GPIO_PF | 9 )#define PA10_PF_CSI_D6 ( GPIO_PORTA | GPIO_PF | 10 )#define PA11_PF_CSI_D7 ( GPIO_PORTA | GPIO_PF | 11 )#define PA12_PF_CSI_VSYNC ( GPIO_PORTA | GPIO_PF | 12 )#define PA13_PF_CSI_HSYNC ( GPIO_PORTA | GPIO_PF | 13 )#define PA14_PF_CSI_PIXCLK ( GPIO_PORTA | GPIO_PF | 14 )#define PA15_PF_I2C_SDA ( GPIO_PORTA | GPIO_OUT | GPIO_PF | 15 )#define PA16_PF_I2C_SCL ( GPIO_PORTA | GPIO_OUT | GPIO_PF | 16 )#define PA17_AF_ETMTRACEPKT4 ( GPIO_PORTA | GPIO_AF | 17 )#define PA17_AIN_SPI2_SS ( GPIO_GIUS | GPIO_PORTA | GPIO_OUT | 17 )#define PA18_AF_ETMTRACEPKT5 ( GPIO_PORTA | GPIO_AF | 18 )#define PA19_AF_ETMTRACEPKT6 ( GPIO_PORTA | GPIO_AF | 19 )#define PA20_AF_ETMTRACEPKT7 ( GPIO_PORTA | GPIO_AF | 20 )#define PA21_PF_A0 ( GPIO_PORTA | GPIO_PF | 21 )#define PA22_PF_CS4 ( GPIO_PORTA | GPIO_PF | 22 )#define PA23_PF_CS5 ( GPIO_PORTA | GPIO_PF | 23 )#define PA24_PF_A16 ( GPIO_PORTA | GPIO_PF | 24 )#define PA24_AF_ETMTRACEPKT0 ( GPIO_PORTA | GPIO_AF | 24 )#define PA25_PF_A17 ( GPIO_PORTA | GPIO_PF | 25 )#define PA25_AF_ETMTRACEPKT1 ( GPIO_PORTA | GPIO_AF | 25 )#define PA26_PF_A18 ( GPIO_PORTA | GPIO_PF | 26 )#define PA26_AF_ETMTRACEPKT2 ( GPIO_PORTA | GPIO_AF | 26 )#define PA27_PF_A19 ( GPIO_PORTA | GPIO_PF | 27 )#define PA27_AF_ETMTRACEPKT3 ( GPIO_PORTA | GPIO_AF | 27 )#define PA28_PF_A20 ( GPIO_PORTA | GPIO_PF | 28 )#define PA28_AF_ETMPIPESTAT0 ( GPIO_PORTA | GPIO_AF | 28 )#define PA29_PF_A21 ( GPIO_PORTA | GPIO_PF | 29 )#define PA29_AF_ETMPIPESTAT1 ( GPIO_PORTA | GPIO_AF | 29 )#define PA30_PF_A22 ( GPIO_PORTA | GPIO_PF | 30 )#define PA30_AF_ETMPIPESTAT2 ( GPIO_PORTA | GPIO_AF | 30 )⌨️ 快捷键说明
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