📄 dpsk.rpt
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Device-Specific Information: g:\pingdai\dpsk\dpsk.rpt
dpsk
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 3 - A 22 DFFE + 0 2 1 0 |PL_CPSK:1|:6
- 2 - A 15 DFFE + 1 1 0 2 |PL_CPSK:1|q1 (|PL_CPSK:1|:8)
- 1 - A 15 DFFE + 1 0 0 2 |PL_CPSK:1|q0 (|PL_CPSK:1|:9)
- 7 - A 15 DFFE + 1 1 1 1 |PL_CPSK:1|f1 (|PL_CPSK:1|:10)
- 5 - A 15 DFFE + 1 1 1 1 |PL_CPSK:1|f2 (|PL_CPSK:1|:11)
- 8 - A 22 OR2 0 3 0 1 |PL_CPSK:1|:224
- 2 - A 22 DFFE + 1 2 1 1 |PL_DPSK:2|:4
- 5 - A 22 DFFE + 1 2 0 1 |PL_DPSK:2|q1 (|PL_DPSK:2|:6)
- 1 - A 22 DFFE + 1 0 0 2 |PL_DPSK:2|q0 (|PL_DPSK:2|:7)
- 7 - A 22 DFFE + 1 2 0 1 |PL_DPSK:2|xx (|PL_DPSK:2|:8)
- 4 - A 22 OR2 ! 0 2 0 4 |PL_DPSK:2|:31
- 6 - A 22 OR2 1 2 0 2 |PL_DPSK:2|:140
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: g:\pingdai\dpsk\dpsk.rpt
dpsk
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 4/ 96( 4%) 0/ 48( 0%) 3/ 48( 6%) 0/16( 0%) 4/16( 25%) 0/16( 0%)
B: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: g:\pingdai\dpsk\dpsk.rpt
dpsk
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 9 CLK
Device-Specific Information: g:\pingdai\dpsk\dpsk.rpt
dpsk
** EQUATIONS **
CLK : INPUT;
DIN : INPUT;
START : INPUT;
-- Node name is 'DOUT'
-- Equation name is 'DOUT', type is output
DOUT = _LC3_A22;
-- Node name is 'DOU1'
-- Equation name is 'DOU1', type is output
DOU1 = _LC2_A22;
-- Node name is 'P1'
-- Equation name is 'P1', type is output
P1 = _LC7_A15;
-- Node name is 'P2'
-- Equation name is 'P2', type is output
P2 = _LC5_A15;
-- Node name is '|PL_CPSK:1|:10' = '|PL_CPSK:1|f1'
-- Equation name is '_LC7_A15', type is buried
_LC7_A15 = DFFE( _EQ001, GLOBAL( CLK), VCC, VCC, VCC);
_EQ001 = _LC7_A15 & !START
# !_LC2_A15 & START;
-- Node name is '|PL_CPSK:1|:11' = '|PL_CPSK:1|f2'
-- Equation name is '_LC5_A15', type is buried
_LC5_A15 = DFFE( _EQ002, GLOBAL( CLK), VCC, VCC, VCC);
_EQ002 = _LC5_A15 & !START
# _LC2_A15 & START;
-- Node name is '|PL_CPSK:1|:9' = '|PL_CPSK:1|q0'
-- Equation name is '_LC1_A15', type is buried
_LC1_A15 = DFFE( _EQ003, GLOBAL( CLK), VCC, VCC, VCC);
_EQ003 = !_LC1_A15 & START;
-- Node name is '|PL_CPSK:1|:8' = '|PL_CPSK:1|q1'
-- Equation name is '_LC2_A15', type is buried
_LC2_A15 = DFFE( _EQ004, GLOBAL( CLK), VCC, VCC, VCC);
_EQ004 = !_LC1_A15 & _LC2_A15 & START
# _LC1_A15 & !_LC2_A15 & START;
-- Node name is '|PL_CPSK:1|:6'
-- Equation name is '_LC3_A22', type is buried
_LC3_A22 = DFFE( _EQ005, GLOBAL( CLK), VCC, VCC, VCC);
_EQ005 = _LC1_A15 & _LC8_A22
# !_LC1_A15 & _LC3_A22;
-- Node name is '|PL_CPSK:1|:224'
-- Equation name is '_LC8_A22', type is buried
_LC8_A22 = LCELL( _EQ006);
_EQ006 = _LC2_A22 & _LC7_A15
# !_LC2_A22 & _LC5_A15;
-- Node name is '|PL_DPSK:2|:7' = '|PL_DPSK:2|q0'
-- Equation name is '_LC1_A22', type is buried
_LC1_A22 = DFFE( _EQ007, GLOBAL( CLK), VCC, VCC, VCC);
_EQ007 = !_LC1_A22 & START;
-- Node name is '|PL_DPSK:2|:6' = '|PL_DPSK:2|q1'
-- Equation name is '_LC5_A22', type is buried
_LC5_A22 = DFFE( _EQ008, GLOBAL( CLK), VCC, VCC, VCC);
_EQ008 = _LC1_A22 & !_LC4_A22 & !_LC5_A22 & START
# !_LC1_A22 & !_LC4_A22 & _LC5_A22 & START;
-- Node name is '|PL_DPSK:2|:8' = '|PL_DPSK:2|xx'
-- Equation name is '_LC7_A22', type is buried
_LC7_A22 = DFFE( _EQ009, GLOBAL( CLK), VCC, VCC, VCC);
_EQ009 = _LC6_A22 & START
# !_LC4_A22 & _LC7_A22 & START;
-- Node name is '|PL_DPSK:2|:4'
-- Equation name is '_LC2_A22', type is buried
_LC2_A22 = DFFE( _EQ010, GLOBAL( CLK), VCC, VCC, VCC);
_EQ010 = _LC2_A22 & !START
# _LC2_A22 & !_LC4_A22
# _LC6_A22 & START;
-- Node name is '|PL_DPSK:2|:31'
-- Equation name is '_LC4_A22', type is buried
!_LC4_A22 = _LC4_A22~NOT;
_LC4_A22~NOT = LCELL( _EQ011);
_EQ011 = _LC1_A22
# _LC5_A22;
-- Node name is '|PL_DPSK:2|:140'
-- Equation name is '_LC6_A22', type is buried
_LC6_A22 = LCELL( _EQ012);
_EQ012 = DIN & _LC4_A22 & !_LC7_A22
# !DIN & _LC4_A22 & _LC7_A22;
Project Information g:\pingdai\dpsk\dpsk.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'ACEX1K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:01
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:02
Fitter 00:00:03
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:06
Memory Allocated
-----------------
Peak memory allocated during compilation = 15,181K
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