📄 dpsk2.rpt
字号:
- 1 - A 18 DFFE + 1 0 0 2 |PL_DPSK2:4|q0 (|PL_DPSK2:4|:7)
- 4 - A 18 DFFE + 0 2 0 1 |PL_DPSK2:4|xx (|PL_DPSK2:4|:8)
- 3 - A 18 OR2 s 1 2 0 2 |PL_DPSK2:4|~110~1
- 4 - A 23 DFFE + 1 2 0 1 |PL_DPSK:3|:4
- 4 - A 24 DFFE + 1 2 0 1 |PL_DPSK:3|q1 (|PL_DPSK:3|:6)
- 3 - A 24 DFFE + 1 0 0 2 |PL_DPSK:3|q0 (|PL_DPSK:3|:7)
- 5 - A 24 DFFE + 1 2 0 1 |PL_DPSK:3|xx (|PL_DPSK:3|:8)
- 8 - A 24 OR2 ! 0 2 0 4 |PL_DPSK:3|:31
- 1 - A 24 OR2 1 2 0 2 |PL_DPSK:3|:140
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: g:\pingdai\dpsk\dpsk2.rpt
dpsk2
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 5/ 96( 5%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
B: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: g:\pingdai\dpsk\dpsk2.rpt
dpsk2
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 16 clk
Device-Specific Information: g:\pingdai\dpsk\dpsk2.rpt
dpsk2
** EQUATIONS **
clk : INPUT;
din : INPUT;
start : INPUT;
-- Node name is 'y'
-- Equation name is 'y', type is output
y = _LC7_A18;
-- Node name is '|PL_CPSK:1|:10' = '|PL_CPSK:1|f1'
-- Equation name is '_LC3_A23', type is buried
_LC3_A23 = DFFE( _EQ001, GLOBAL( clk), VCC, VCC, VCC);
_EQ001 = _LC3_A23 & !start
# !_LC2_A23 & start;
-- Node name is '|PL_CPSK:1|:11' = '|PL_CPSK:1|f2'
-- Equation name is '_LC5_A23', type is buried
_LC5_A23 = DFFE( _EQ002, GLOBAL( clk), VCC, VCC, VCC);
_EQ002 = _LC5_A23 & !start
# _LC2_A23 & start;
-- Node name is '|PL_CPSK:1|:9' = '|PL_CPSK:1|q0'
-- Equation name is '_LC6_A23', type is buried
_LC6_A23 = DFFE( _EQ003, GLOBAL( clk), VCC, VCC, VCC);
_EQ003 = !_LC6_A23 & start;
-- Node name is '|PL_CPSK:1|:8' = '|PL_CPSK:1|q1'
-- Equation name is '_LC2_A23', type is buried
_LC2_A23 = DFFE( _EQ004, GLOBAL( clk), VCC, VCC, VCC);
_EQ004 = _LC2_A23 & !_LC6_A23 & start
# !_LC2_A23 & _LC6_A23 & start;
-- Node name is '|PL_CPSK:1|:6'
-- Equation name is '_LC8_A23', type is buried
_LC8_A23 = DFFE( _EQ005, GLOBAL( clk), VCC, VCC, VCC);
_EQ005 = _LC6_A23 & _LC7_A23
# !_LC6_A23 & _LC8_A23;
-- Node name is '|PL_CPSK:1|:224'
-- Equation name is '_LC7_A23', type is buried
_LC7_A23 = LCELL( _EQ006);
_EQ006 = _LC3_A23 & _LC4_A23
# !_LC4_A23 & _LC5_A23;
-- Node name is '|PL_CPSK2:2|:7' = '|PL_CPSK2:2|q0'
-- Equation name is '_LC6_A24', type is buried
_LC6_A24 = DFFE( _EQ007, GLOBAL( clk), VCC, VCC, VCC);
_EQ007 = !_LC6_A24 & start;
-- Node name is '|PL_CPSK2:2|:6' = '|PL_CPSK2:2|q1'
-- Equation name is '_LC7_A24', type is buried
_LC7_A24 = DFFE( _EQ008, GLOBAL( clk), VCC, VCC, VCC);
_EQ008 = !_LC2_A24 & !_LC6_A24 & _LC7_A24 & start
# !_LC2_A24 & _LC6_A24 & !_LC7_A24 & start;
-- Node name is '|PL_CPSK2:2|:4'
-- Equation name is '_LC1_A23', type is buried
_LC1_A23 = DFFE( _EQ009, GLOBAL( clk), VCC, VCC, VCC);
_EQ009 = _LC2_A24 & _LC8_A23 & start
# _LC1_A23 & !start
# _LC1_A23 & !_LC2_A24;
-- Node name is '|PL_CPSK2:2|:30'
-- Equation name is '_LC2_A24', type is buried
!_LC2_A24 = _LC2_A24~NOT;
_LC2_A24~NOT = LCELL( _EQ010);
_EQ010 = _LC6_A24
# _LC7_A24;
-- Node name is '|PL_DPSK2:4|:7' = '|PL_DPSK2:4|q0'
-- Equation name is '_LC1_A18', type is buried
_LC1_A18 = DFFE( _EQ011, GLOBAL( clk), VCC, VCC, VCC);
_EQ011 = !_LC1_A18 & start;
-- Node name is '|PL_DPSK2:4|:6' = '|PL_DPSK2:4|q1'
-- Equation name is '_LC2_A18', type is buried
_LC2_A18 = DFFE( _EQ012, GLOBAL( clk), VCC, VCC, VCC);
_EQ012 = _LC1_A18 & !_LC2_A18 & start
# !_LC1_A18 & _LC2_A18 & start;
-- Node name is '|PL_DPSK2:4|:8' = '|PL_DPSK2:4|xx'
-- Equation name is '_LC4_A18', type is buried
_LC4_A18 = DFFE( _EQ013, GLOBAL( clk), VCC, VCC, VCC);
_EQ013 = !_LC1_A23 & !_LC3_A18
# _LC3_A18 & _LC4_A18;
-- Node name is '|PL_DPSK2:4|:4'
-- Equation name is '_LC7_A18', type is buried
_LC7_A18 = DFFE( _EQ014, GLOBAL( clk), VCC, VCC, VCC);
_EQ014 = _LC3_A18 & _LC7_A18
# !_LC1_A23 & !_LC3_A18 & !_LC4_A18
# _LC1_A23 & !_LC3_A18 & _LC4_A18;
-- Node name is '|PL_DPSK2:4|~110~1'
-- Equation name is '_LC3_A18', type is buried
-- synthesized logic cell
_LC3_A18 = LCELL( _EQ015);
_EQ015 = !start
# !_LC1_A18
# !_LC2_A18;
-- Node name is '|PL_DPSK:3|:7' = '|PL_DPSK:3|q0'
-- Equation name is '_LC3_A24', type is buried
_LC3_A24 = DFFE( _EQ016, GLOBAL( clk), VCC, VCC, VCC);
_EQ016 = !_LC3_A24 & start;
-- Node name is '|PL_DPSK:3|:6' = '|PL_DPSK:3|q1'
-- Equation name is '_LC4_A24', type is buried
_LC4_A24 = DFFE( _EQ017, GLOBAL( clk), VCC, VCC, VCC);
_EQ017 = _LC3_A24 & !_LC4_A24 & !_LC8_A24 & start
# !_LC3_A24 & _LC4_A24 & !_LC8_A24 & start;
-- Node name is '|PL_DPSK:3|:8' = '|PL_DPSK:3|xx'
-- Equation name is '_LC5_A24', type is buried
_LC5_A24 = DFFE( _EQ018, GLOBAL( clk), VCC, VCC, VCC);
_EQ018 = _LC1_A24 & start
# _LC5_A24 & !_LC8_A24 & start;
-- Node name is '|PL_DPSK:3|:4'
-- Equation name is '_LC4_A23', type is buried
_LC4_A23 = DFFE( _EQ019, GLOBAL( clk), VCC, VCC, VCC);
_EQ019 = _LC4_A23 & !start
# _LC4_A23 & !_LC8_A24
# _LC1_A24 & start;
-- Node name is '|PL_DPSK:3|:31'
-- Equation name is '_LC8_A24', type is buried
!_LC8_A24 = _LC8_A24~NOT;
_LC8_A24~NOT = LCELL( _EQ020);
_EQ020 = _LC3_A24
# _LC4_A24;
-- Node name is '|PL_DPSK:3|:140'
-- Equation name is '_LC1_A24', type is buried
_LC1_A24 = LCELL( _EQ021);
_EQ021 = din & !_LC5_A24 & _LC8_A24
# !din & _LC5_A24 & _LC8_A24;
Project Information g:\pingdai\dpsk\dpsk2.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'ACEX1K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:02
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:01
Fitter 00:00:02
Timing SNF Extractor 00:00:00
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:06
Memory Allocated
-----------------
Peak memory allocated during compilation = 17,979K
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