nand0_1.vhd

来自「描述了DPSK的整个程序」· VHDL 代码 · 共 12 行

library ieee;
Use ieee.std_logic_1164.all;
entity nand0_1 is
  port(X2:in std_logic;
       out2:out std_logic);
end entity nand0_1;
architecture nand_0 of nand0_1 is
begin
      out2<=not X2;
end architecture nand_0;