stm32f10x_map.h

通过手动烧写flash,实现了stm32的自动更新功能,用户可以再本例程的基础上修改实现通过串口或者网络实现程序的自动更新

/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
* File Name          : stm32f10x_map.h
* Author             : MCD Application Team
* Date First Issued  : 09/29/2006
* Description        : This file contains all the peripheral register's definitions
*                      and memory mapping.
********************************************************************************
* History:
* 05/21/2007: V0.3
* 04/02/2007: V0.2
* 02/05/2007: V0.1
* 09/29/2006: V0.01
********************************************************************************
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/

/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F10x_MAP_H
#define __STM32F10x_MAP_H

#ifndef EXT
  #define EXT extern
#endif /* EXT */

/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_conf.h"
#include "stm32f10x_type.h"
#include "cortexm3_macro.h"

/* Exported types ------------------------------------------------------------*/
/******************************************************************************/
/*                          IP registers structures                           */
/******************************************************************************/

/*------------------------ Analog to Digital Converter -----------------------*/
typedef struct
{
  INT32UC SR;
  INT32UC CR1;
  INT32UC CR2;
  INT32UC SMPR1;
  INT32UC SMPR2;
  INT32UC JOFR1;
  INT32UC JOFR2;
  INT32UC JOFR3;
  INT32UC JOFR4;
  INT32UC HTR;
  INT32UC LTR;
  INT32UC SQR1;
  INT32UC SQR2;
  INT32UC SQR3;
  INT32UC JSQR;
  INT32UC JDR1;
  INT32UC JDR2;
  INT32UC JDR3;
  INT32UC JDR4;
  INT32UC DR;
} ADC_TypeDef;

/*------------------------ Backup Registers ----------------------------------*/
typedef struct
{
  INT32U RESERVED0;
  INT16UC DR1;
  INT16U  RESERVED1;
  INT16UC DR2;
  INT16U  RESERVED2;
  INT16UC DR3;
  INT16U  RESERVED3;
  INT16UC DR4;
  INT16U  RESERVED4;
  INT16UC DR5;
  INT16U  RESERVED5;
  INT16UC DR6;
  INT16U  RESERVED6;
  INT16UC DR7;
  INT16U  RESERVED7;
  INT16UC DR8;
  INT16U  RESERVED8;
  INT16UC DR9;
  INT16U  RESERVED9;
  INT16UC DR10;
  INT16U  RESERVED10;
  INT16UC RTCCR;
  INT16U  RESERVED11;
  INT16UC CR;
  INT16U  RESERVED12;
  INT16UC CSR;
  INT16U  RESERVED13;
} BKP_TypeDef;

/*------------------------ Controller Area Network ---------------------------*/
typedef struct
{
  INT32UC TIR;
  INT32UC TDTR;
  INT32UC TDLR;
  INT32UC TDHR;
} CAN_TxMailBox_TypeDef;

typedef struct
{
  INT32UC RIR;
  INT32UC RDTR;
  INT32UC RDLR;
  INT32UC RDHR;
} CAN_FIFOMailBox_TypeDef;

typedef struct
{
  INT32UC FR0;
  INT32UC FR1;
} CAN_FilterRegister_TypeDef;

typedef struct
{
  INT32UC MCR;
  INT32UC MSR;
  INT32UC TSR;
  INT32UC RF0R;
  INT32UC RF1R;
  INT32UC IER;
  INT32UC ESR;
  INT32UC BTR;
  INT32U RESERVED0[88];
  CAN_TxMailBox_TypeDef sTxMailBox[3];
  CAN_FIFOMailBox_TypeDef sFIFOMailBox[2];
  INT32U RESERVED1[12];
  INT32UC FMR;
  INT32UC FM0R;
  INT32U RESERVED2[1];
  INT32UC FS0R;
  INT32U RESERVED3[1];
  INT32UC FFA0R;
  INT32U RESERVED4[1];
  INT32UC FA0R;
  INT32U RESERVED5[8];
  CAN_FilterRegister_TypeDef sFilterRegister[14];
} CAN_TypeDef;

/*------------------------ DMA Controller ------------------------------------*/
typedef struct
{
  INT32UC CCR;
  INT32UC CNDTR;
  INT32UC CPAR;
  INT32UC CMAR;
} DMA_Channel_TypeDef;

typedef struct
{
  INT32UC ISR;
  INT32UC IFCR;
} DMA_TypeDef;

/*------------------------ External Interrupt/Event Controller ---------------*/
typedef struct
{
  INT32UC IMR;
  INT32UC EMR;
  INT32UC RTSR;
  INT32UC FTSR;
  INT32UC SWIER;
  INT32UC PR;
} EXTI_TypeDef;

/*------------------------ FLASH and Option Bytes Registers ------------------*/
typedef struct
{
  INT32UC ACR;
  INT32UC KEYR;
  INT32UC OPTKEYR;
  INT32UC SR;
  INT32UC CR;
  INT32UC AR;
  INT32UC RESERVED;
  INT32UC OBR;
  INT32UC WRPR;
} FLASH_TypeDef;

typedef struct
{
  INT16UC RDP;
  INT16UC USER;
  INT16UC Data0;
  INT16UC Data1;
  INT16UC WRP0;
  INT16UC WRP1;
  INT16UC WRP2;
  INT16UC WRP3;
} OB_TypeDef;

/*------------------------ General Purpose and Alternate Function IO ---------*/
typedef struct
{
  INT32UC CRL;
  INT32UC CRH;
  INT32UC IDR;
  INT32UC ODR;
  INT32UC BSRR;
  INT32UC BRR;
  INT32UC LCKR;
} GPIO_TypeDef;

typedef struct
{
  INT32UC EVCR;
  INT32UC MAPR;
  INT32UC EXTICR[4];
} AFIO_TypeDef;

/*------------------------ Inter-integrated Circuit Interface ----------------*/
typedef struct
{
  INT16UC CR1;
  INT16U RESERVED0;
  INT16UC CR2;
  INT16U RESERVED1;
  INT16UC OAR1;
  INT16U RESERVED2;
  INT16UC OAR2;
  INT16U RESERVED3;
  INT16UC DR;
  INT16U RESERVED4;
  INT16UC SR1;
  INT16U RESERVED5;
  INT16UC SR2;
  INT16U RESERVED6;
  INT16UC CCR;
  INT16U RESERVED7;
  INT16UC TRISE;
  INT16U RESERVED8;
} I2C_TypeDef;

/*------------------------ Independent WATCHDOG ------------------------------*/
typedef struct
{
  INT32UC KR;
  INT32UC PR;
  INT32UC RLR;
  INT32UC SR;
} IWDG_TypeDef;

/*------------------------ Nested Vectored Interrupt Controller --------------*/
typedef struct
{
  INT32UC Enable[2];
  INT32U RESERVED0[30];
  INT32UC Disable[2];
  INT32U RSERVED1[30];
  INT32UC Set[2];
  INT32U RESERVED2[30];
  INT32UC Clear[2];
  INT32U RESERVED3[30];
  INT32UC Active[2];
  INT32U RESERVED4[62];
  INT32UC Priority[11];
} NVIC_TypeDef;

typedef struct
{
  INT32UC CPUID;
  INT32UC IRQControlState;
  INT32UC ExceptionTableOffset;
  INT32UC AIRC;
  INT32UC SysCtrl;
  INT32UC ConfigCtrl;
  INT32UC SystemPriority[3];
  INT32UC SysHandlerCtrl;
  INT32UC ConfigFaultStatus;
  INT32UC HardFaultStatus;
  INT32UC DebugFaultStatus;
  INT32UC MemoryManageFaultAddr;
  INT32UC BusFaultAddr;
} SCB_TypeDef;

/*------------------------ Power Control -------------------------------------*/
typedef struct
{
  INT32UC CR;
  INT32UC CSR;
} PWR_TypeDef;

/*------------------------ Reset and Clock Control ---------------------------*/
typedef struct
{
  INT32UC CR;
  INT32UC CFGR;
  INT32UC CIR;
  INT32UC APB2RSTR;
  INT32UC APB1RSTR;
  INT32UC AHBENR;
  INT32UC APB2ENR;
  INT32UC APB1ENR;
  INT32UC BDCR;
  INT32UC CSR;
} RCC_TypeDef;

/*------------------------ Real-Time Clock -----------------------------------*/
typedef struct
{
  INT16UC CRH;
  INT16U RESERVED0;
  INT16UC CRL;
  INT16U RESERVED1;
  INT16UC PRLH;
  INT16U RESERVED2;
  INT16UC PRLL;
  INT16U RESERVED3;
  INT16UC DIVH;
  INT16U RESERVED4;
  INT16UC DIVL;
  INT16U RESERVED5;
  INT16UC CNTH;
  INT16U RESERVED6;
  INT16UC CNTL;
  INT16U RESERVED7;
  INT16UC ALRH;
  INT16U RESERVED8;
  INT16UC ALRL;
  INT16U RESERVED9;
} RTC_TypeDef;

/*------------------------ Serial Peripheral Interface -----------------------*/
typedef struct
{
  INT16UC CR1;
  INT16U RESERVED0;
  INT16UC CR2;
  INT16U RESERVED1;
  INT16UC SR;
  INT16U  RESERVED2;
  INT16UC DR;
  INT16U  RESERVED3;
  INT16UC CRCPR;
  INT16U RESERVED4;
  INT16UC RXCRCR;
  INT16U  RESERVED5;
  INT16UC TXCRCR;
  INT16U  RESERVED6;
} SPI_TypeDef;

/*------------------------ SystemTick ----------------------------------------*/
typedef struct
{
  INT32UC CTRL;
  INT32UC LOAD;
  INT32UC VAL;
  VINT32UC CALIB;
} SysTick_TypeDef;

/*------------------------ Advanced Control Timer ----------------------------*/
typedef struct
{
  INT16UC CR1;
  INT16U RESERVED0;
  INT16UC CR2;
  INT16U RESERVED1;
  INT16UC SMCR;
  INT16U RESERVED2;
  INT16UC DIER;
  INT16U RESERVED3;
  INT16UC SR;
  INT16U RESERVED4;
  INT16UC EGR;
  INT16U RESERVED5;
  INT16UC CCMR1;
  INT16U RESERVED6;
  INT16UC CCMR2;
  INT16U RESERVED7;
  INT16UC CCER;
  INT16U RESERVED8;
  INT16UC CNT;
  INT16U RESERVED9;
  INT16UC PSC;
  INT16U RESERVED10;
  INT16UC ARR;
  INT16U RESERVED11;
  INT16UC RCR;
  INT16U RESERVED12;
  INT16UC CCR1;
  INT16U RESERVED13;
  INT16UC CCR2;
  INT16U RESERVED14;
  INT16UC CCR3;
  INT16U RESERVED15;
  INT16UC CCR4;
  INT16U RESERVED16;
  INT16UC BDTR;
  INT16U RESERVED17;
  INT16UC DCR;
  INT16U RESERVED18;
  INT16UC DMAR;
  INT16U RESERVED19;
} TIM1_TypeDef;

/*------------------------ General Purpose Timer -----------------------------*/
typedef struct
{
  INT16UC CR1;
  INT16U RESERVED0;
  INT16UC CR2;
  INT16U RESERVED1;
  INT16UC SMCR;
  INT16U RESERVED2;
  INT16UC DIER;
  INT16U RESERVED3;
  INT16UC SR;
  INT16U RESERVED4;
  INT16UC EGR;
  INT16U RESERVED5;
  INT16UC CCMR1;
  INT16U RESERVED6;
  INT16UC CCMR2;
  INT16U RESERVED7;
  INT16UC CCER;
  INT16U RESERVED8;
  INT16UC CNT;
  INT16U RESERVED9;
  INT16UC PSC;
  INT16U RESERVED10;
  INT16UC ARR;
  INT16U RESERVED11[3];
  INT16UC CCR1;
  INT16U RESERVED12;
  INT16UC CCR2;