project3.tan.qmsg

用VHDL语言实现一个10秒倒计时电路

{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "3 " "Warning: Found 3 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "cou1 " "Info: Detected ripple clock \"cou1\" as buffer" {  } { { "project3.vhd" "" { Text "E:/project3/project3.vhd" 19 -1 0 } } { "d:/program files/quartusii/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/program files/quartusii/quartus/bin/Assignment Editor.qase" 1 { { 0 "cou1" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "clk2 " "Info: Detected ripple clock \"clk2\" as buffer" {  } { { "project3.vhd" "" { Text "E:/project3/project3.vhd" 17 -1 0 } } { "d:/program files/quartusii/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/program files/quartusii/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk2" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "clk1 " "Info: Detected ripple clock \"clk1\" as buffer" {  } { { "project3.vhd" "" { Text "E:/project3/project3.vhd" 17 -1 0 } } { "d:/program files/quartusii/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/program files/quartusii/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk1" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register ctrl_c\[1\] register alarm~reg0 59.72 MHz 16.744 ns Internal " "Info: Clock \"clk\" has Internal fmax of 59.72 MHz between source register \"ctrl_c\[1\]\" and destination register \"alarm~reg0\" (period= 16.744 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.485 ns + Longest register register " "Info: + Longest register to register delay is 2.485 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns ctrl_c\[1\] 1 REG LC_X8_Y7_N4 9 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X8_Y7_N4; Fanout = 9; REG Node = 'ctrl_c\[1\]'" {  } { { "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "" { ctrl_c[1] } "NODE_NAME" } } { "project3.vhd" "" { Text "E:/project3/project3.vhd" 57 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.078 ns) + CELL(0.511 ns) 1.589 ns Equal3~62 2 COMB LC_X8_Y7_N1 2 " "Info: 2: + IC(1.078 ns) + CELL(0.511 ns) = 1.589 ns; Loc. = LC_X8_Y7_N1; Fanout = 2; COMB Node = 'Equal3~62'" {  } { { "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "1.589 ns" { ctrl_c[1] Equal3~62 } "NODE_NAME" } } { "project3.vhd" "" { Text "E:/project3/project3.vhd" 70 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.305 ns) + CELL(0.591 ns) 2.485 ns alarm~reg0 3 REG LC_X8_Y7_N2 3 " "Info: 3: + IC(0.305 ns) + CELL(0.591 ns) = 2.485 ns; Loc. = LC_X8_Y7_N2; Fanout = 3; REG Node = 'alarm~reg0'" {  } { { "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "0.896 ns" { Equal3~62 alarm~reg0 } "NODE_NAME" } } { "project3.vhd" "" { Text "E:/project3/project3.vhd" 75 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.102 ns ( 44.35 % ) " "Info: Total cell delay = 1.102 ns ( 44.35 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.383 ns ( 55.65 % ) " "Info: Total interconnect delay = 1.383 ns ( 55.65 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "2.485 ns" { ctrl_c[1] Equal3~62 alarm~reg0 } "NODE_NAME" } } { "d:/program files/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/quartusii/quartus/bin/Technology_Viewer.qrui" "2.485 ns" { ctrl_c[1] {} Equal3~62 {} alarm~reg0 {} } { 0.000ns 1.078ns 0.305ns } { 0.000ns 0.511ns 0.591ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-5.178 ns - Smallest " "Info: - Smallest clock skew is -5.178 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 8.715 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 8.715 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_18 39 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 39; CLK Node = 'clk'" {  } { { "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "project3.vhd" "" { Text "E:/project3/project3.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.738 ns) + CELL(1.294 ns) 4.195 ns clk2 2 REG LC_X15_Y3_N2 6 " "Info: 2: + IC(1.738 ns) + CELL(1.294 ns) = 4.195 ns; Loc. = LC_X15_Y3_N2; Fanout = 6; REG Node = 'clk2'" {  } { { "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "3.032 ns" { clk clk2 } "NODE_NAME" } } { "project3.vhd" "" { Text "E:/project3/project3.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.602 ns) + CELL(0.918 ns) 8.715 ns alarm~reg0 3 REG LC_X8_Y7_N2 3 " "Info: 3: + IC(3.602 ns) + CELL(0.918 ns) = 8.715 ns; Loc. = LC_X8_Y7_N2; Fanout = 3; REG Node = 'alarm~reg0'" {  } { { "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "4.520 ns" { clk2 alarm~reg0 } "NODE_NAME" } } { "project3.vhd" "" { Text "E:/project3/project3.vhd" 75 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.375 ns ( 38.73 % ) " "Info: Total cell delay = 3.375 ns ( 38.73 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.340 ns ( 61.27 % ) " "Info: Total interconnect delay = 5.340 ns ( 61.27 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "8.715 ns" { clk clk2 alarm~reg0 } "NODE_NAME" } } { "d:/program files/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/quartusii/quartus/bin/Technology_Viewer.qrui" "8.715 ns" { clk {} clk~combout {} clk2 {} alarm~reg0 {} } { 0.000ns 0.000ns 1.738ns 3.602ns } { 0.000ns 1.163ns 1.294ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 13.893 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 13.893 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_18 39 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 39; CLK Node = 'clk'" {  } { { "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "project3.vhd" "" { Text "E:/project3/project3.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.738 ns) + CELL(1.294 ns) 4.195 ns clk1 2 REG LC_X12_Y3_N9 22 " "Info: 2: + IC(1.738 ns) + CELL(1.294 ns) = 4.195 ns; Loc. = LC_X12_Y3_N9; Fanout = 22; REG Node = 'clk1'" {  } { { "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "3.032 ns" { clk clk1 } "NODE_NAME" } } { "project3.vhd" "" { Text "E:/project3/project3.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.023 ns) + CELL(1.294 ns) 8.512 ns cou1 3 REG LC_X10_Y4_N4 3 " "Info: 3: + IC(3.023 ns) + CELL(1.294 ns) = 8.512 ns; Loc. = LC_X10_Y4_N4; Fanout = 3; REG Node = 'cou1'" {  } { { "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "4.317 ns" { clk1 cou1 } "NODE_NAME" } } { "project3.vhd" "" { Text "E:/project3/project3.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.463 ns) + CELL(0.918 ns) 13.893 ns ctrl_c\[1\] 4 REG LC_X8_Y7_N4 9 " "Info: 4: + IC(4.463 ns) + CELL(0.918 ns) = 13.893 ns; Loc. = LC_X8_Y7_N4; Fanout = 9; REG Node = 'ctrl_c\[1\]'" {  } { { "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "5.381 ns" { cou1 ctrl_c[1] } "NODE_NAME" } } { "project3.vhd" "" { Text "E:/project3/project3.vhd" 57 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.669 ns ( 33.61 % ) " "Info: Total cell delay = 4.669 ns ( 33.61 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "9.224 ns ( 66.39 % ) " "Info: Total interconnect delay = 9.224 ns ( 66.39 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "13.893 ns" { clk clk1 cou1 ctrl_c[1] } "NODE_NAME" } } { "d:/program files/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/quartusii/quartus/bin/Technology_Viewer.qrui" "13.893 ns" { clk {} clk~combout {} clk1 {} cou1 {} ctrl_c[1] {} } { 0.000ns 0.000ns 1.738ns 3.023ns 4.463ns } { 0.000ns 1.163ns 1.294ns 1.294ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "8.715 ns" { clk clk2 alarm~reg0 } "NODE_NAME" } } { "d:/program files/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/quartusii/quartus/bin/Technology_Viewer.qrui" "8.715 ns" { clk {} clk~combout {} clk2 {} alarm~reg0 {} } { 0.000ns 0.000ns 1.738ns 3.602ns } { 0.000ns 1.163ns 1.294ns 0.918ns } "" } } { "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "13.893 ns" { clk clk1 cou1 ctrl_c[1] } "NODE_NAME" } } { "d:/program files/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/quartusii/quartus/bin/Technology_Viewer.qrui" "13.893 ns" { clk {} clk~combout {} clk1 {} cou1 {} ctrl_c[1] {} } { 0.000ns 0.000ns 1.738ns 3.023ns 4.463ns } { 0.000ns 1.163ns 1.294ns 1.294ns 0.918ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" {  } { { "project3.vhd" "" { Text "E:/project3/project3.vhd" 57 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" {  } { { "project3.vhd" "" { Text "E:/project3/project3.vhd" 75 0 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" {  } { { "project3.vhd" "" { Text "E:/project3/project3.vhd" 57 -1 0 } } { "project3.vhd" "" { Text "E:/project3/project3.vhd" 75 0 0 } }  } 0 0 "Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" 0 0 "" 0}  } { { "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "2.485 ns" { ctrl_c[1] Equal3~62 alarm~reg0 } "NODE_NAME" } } { "d:/program files/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/quartusii/quartus/bin/Technology_Viewer.qrui" "2.485 ns" { ctrl_c[1] {} Equal3~62 {} alarm~reg0 {} } { 0.000ns 1.078ns 0.305ns } { 0.000ns 0.511ns 0.591ns } "" } } { "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "8.715 ns" { clk clk2 alarm~reg0 } "NODE_NAME" } } { "d:/program files/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/quartusii/quartus/bin/Technology_Viewer.qrui" "8.715 ns" { clk {} clk~combout {} clk2 {} alarm~reg0 {} } { 0.000ns 0.000ns 1.738ns 3.602ns } { 0.000ns 1.163ns 1.294ns 0.918ns } "" } } { "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "13.893 ns" { clk clk1 cou1 ctrl_c[1] } "NODE_NAME" } } { "d:/program files/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/quartusii/quartus/bin/Technology_Viewer.qrui" "13.893 ns" { clk {} clk~combout {} clk1 {} cou1 {} ctrl_c[1] {} } { 0.000ns 0.000ns 1.738ns 3.023ns 4.463ns } { 0.000ns 1.163ns 1.294ns 1.294ns 0.918ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk alarm alarm~reg0 13.652 ns register " "Info: tco from clock \"clk\" to destination pin \"alarm\" through register \"alarm~reg0\" is 13.652 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 8.715 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 8.715 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_18 39 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 39; CLK Node = 'clk'" {  } { { "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "project3.vhd" "" { Text "E:/project3/project3.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.738 ns) + CELL(1.294 ns) 4.195 ns clk2 2 REG LC_X15_Y3_N2 6 " "Info: 2: + IC(1.738 ns) + CELL(1.294 ns) = 4.195 ns; Loc. = LC_X15_Y3_N2; Fanout = 6; REG Node = 'clk2'" {  } { { "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "3.032 ns" { clk clk2 } "NODE_NAME" } } { "project3.vhd" "" { Text "E:/project3/project3.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.602 ns) + CELL(0.918 ns) 8.715 ns alarm~reg0 3 REG LC_X8_Y7_N2 3 " "Info: 3: + IC(3.602 ns) + CELL(0.918 ns) = 8.715 ns; Loc. = LC_X8_Y7_N2; Fanout = 3; REG Node = 'alarm~reg0'" {  } { { "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "4.520 ns" { clk2 alarm~reg0 } "NODE_NAME" } } { "project3.vhd" "" { Text "E:/project3/project3.vhd" 75 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.375 ns ( 38.73 % ) " "Info: Total cell delay = 3.375 ns ( 38.73 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.340 ns ( 61.27 % ) " "Info: Total interconnect delay = 5.340 ns ( 61.27 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "8.715 ns" { clk clk2 alarm~reg0 } "NODE_NAME" } } { "d:/program files/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/quartusii/quartus/bin/Technology_Viewer.qrui" "8.715 ns" { clk {} clk~combout {} clk2 {} alarm~reg0 {} } { 0.000ns 0.000ns 1.738ns 3.602ns } { 0.000ns 1.163ns 1.294ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" {  } { { "project3.vhd" "" { Text "E:/project3/project3.vhd" 75 0 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.561 ns + Longest register pin " "Info: + Longest register to pin delay is 4.561 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns alarm~reg0 1 REG LC_X8_Y7_N2 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X8_Y7_N2; Fanout = 3; REG Node = 'alarm~reg0'" {  } { { "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "" { alarm~reg0 } "NODE_NAME" } } { "project3.vhd" "" { Text "E:/project3/project3.vhd" 75 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.239 ns) + CELL(2.322 ns) 4.561 ns alarm 2 PIN PIN_60 0 " "Info: 2: + IC(2.239 ns) + CELL(2.322 ns) = 4.561 ns; Loc. = PIN_60; Fanout = 0; PIN Node = 'alarm'" {  } { { "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "4.561 ns" { alarm~reg0 alarm } "NODE_NAME" } } { "project3.vhd" "" { Text "E:/project3/project3.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.322 ns ( 50.91 % ) " "Info: Total cell delay = 2.322 ns ( 50.91 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.239 ns ( 49.09 % ) " "Info: Total interconnect delay = 2.239 ns ( 49.09 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "4.561 ns" { alarm~reg0 alarm } "NODE_NAME" } } { "d:/program files/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/quartusii/quartus/bin/Technology_Viewer.qrui" "4.561 ns" { alarm~reg0 {} alarm {} } { 0.000ns 2.239ns } { 0.000ns 2.322ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "8.715 ns" { clk clk2 alarm~reg0 } "NODE_NAME" } } { "d:/program files/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/quartusii/quartus/bin/Technology_Viewer.qrui" "8.715 ns" { clk {} clk~combout {} clk2 {} alarm~reg0 {} } { 0.000ns 0.000ns 1.738ns 3.602ns } { 0.000ns 1.163ns 1.294ns 0.918ns } "" } } { "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "4.561 ns" { alarm~reg0 alarm } "NODE_NAME" } } { "d:/program files/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/quartusii/quartus/bin/Technology_Viewer.qrui" "4.561 ns" { alarm~reg0 {} alarm {} } { 0.000ns 2.239ns } { 0.000ns 2.322ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "116 " "Info: Allocated 116 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Wed Dec 24 00:19:54 2008 " "Info: Processing ended: Wed Dec 24 00:19:54 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}