project3.fit.summary

用VHDL语言实现一个10秒倒计时电路

Fitter Status : Successful - Wed Dec 24 00:19:49 2008
Quartus II Version : 7.2 Build 151 09/26/2007 SJ Full Version
Revision Name : project3
Top-level Entity Name : project3
Family : MAX II
Device : EPM1270T144C5
Timing Models : Final
Total logic elements : 146 / 1,270 ( 11 % )
Total pins : 19 / 116 ( 16 % )
Total virtual pins : 0
UFM blocks : 0 / 1 ( 0 % )