📄 video_test.c
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/*
* Copyright 2005 by Spectrum Digital Incorporated.
* All rights reserved. Property of Spectrum Digital Incorporated.
*
* Not for distribution.
*/
/*
* Video Loopback Test
*
*/
#include "davincievm_i2c.h"
#include "csl_emif.h"
#include "cslr_emif.h"
#define TVP5146_I2C_ADDR 0x5D
#define REF_RATE 0x0190
#define CAS_LATENCY 3
#define INT_BANKS 4
CSL_EmifHandle hEmif = NULL;
Uint32 emifExampleFailed = 0;
void emif_SDRAM_tranfer (Uint32 *eSdramData, Uint32 *eSdramDatab, Uint32 DATA_COUNT)
{
Uint32 loopIndex =1;
for(loopIndex=0; loopIndex<DATA_COUNT; loopIndex=loopIndex+4)
*( volatile Uint32* )(*eSdramDatab+loopIndex) = *( volatile Uint32* )(*eSdramData+loopIndex) ;
}
/* ------------------------------------------------------------------------ *
* *
* tvp5146_rset *
* *
* Set codec register regnum to value regval *
* *
* ------------------------------------------------------------------------ */
void tvp5146_rset( Uint8 regnum, Uint8 regval )
{
Uint8 cmd[2];
cmd[0] = regnum; // 8-bit Register Address
cmd[1] = regval; // 8-bit Register Data
DAVINCIEVM_I2C_write( TVP5146_I2C_ADDR, cmd, 2 );
}
/* ------------------------------------------------------------------------ *
* *
* tvp5146_rget *
* *
* Return value of codec register regnum *
* *
* ------------------------------------------------------------------------ */
Uint8 tvp5146_rget( Uint8 regnum )
{
Uint8 cmd[2];
cmd[0] = regnum; // 8-bit Register Address
cmd[1] = 0; // 8-bit Register Data
DAVINCIEVM_I2C_write( TVP5146_I2C_ADDR, cmd, 1 );
DAVINCIEVM_I2C_read ( TVP5146_I2C_ADDR, cmd, 1 );
return cmd[0];
}
/* ------------------------------------------------------------------------ *
* *
* tvp5146_init( ) *
* *
* Initialize the TVP5146 *
* *
* ------------------------------------------------------------------------ */
void tvp5146_init( )
{
DAVINCIEVM_waitusec( 1000 ); // wait 1 msec
tvp5146_rset( 0xE8, 0x02 ); // Initalize TVP5146, must do after power on
tvp5146_rset( 0xE9, 0x00 );
tvp5146_rset( 0xEA, 0x80 );
tvp5146_rset( 0xE0, 0x01 );
tvp5146_rset( 0xE8, 0x60 );
tvp5146_rset( 0xE9, 0x00 );
tvp5146_rset( 0xEA, 0xB0 );
tvp5146_rset( 0xE0, 0x01 );
tvp5146_rset( 0xE0, 0x00 );
DAVINCIEVM_waitusec( 1000 ); // wait 1 msec
tvp5146_rset( 0x00, 0x05 ); // Input Video: CVBS : VI_2_B
//tvp5146_rset( 0x00, 0x46 ); // Input Video: S-video: VI_2_C(Y) VI_1_C(C)
tvp5146_rset( 0x01, 0x0f ); // AFE Gain Control Register (Automatic gain)
tvp5146_rset( 0x02, 0x01 ); // 0x01 NTSC (component 525)
// 0x02 PAL (component 625) ...etc.
tvp5146_rset( 0x05, 0x00 ); // Color Killer Register "default =00"
//tvp5146 :: OUTPUT format register.
tvp5146_rset( 0x33, 0x40 ); // Extended coding rage (Y,Cb and Cr range from 4 to 1016)
// output format = 10-bit 4:2:2 with embedded syncs(ITU-R BT565)
tvp5146_rset( 0x34, 0x11 ); // Enabling clock & Y/CB/CR input format
DAVINCIEVM_waitusec( 1000 ); // wait 1 msec
}
#define NTSC 1
#if NTSC
#define BASEP_X 0x7A // 122
#define BASEP_Y 0x12 // 18
#elif PAL
#define BASEP_X 0x84 // 132
#define BASEP_Y 0x16 // 22
#endif
/* ------------------------------------------------------------------------ *
* *
* vpfe_init( ) *
* *
* NTSC: *
* Width: 720 *
* Height: 480 *
* *
* *
* ------------------------------------------------------------------------ */
void vpfe_init( Uint32 buffer, Uint32 width, Uint32 height )
{
VPFE_SYN_MODE = 0x00032F84; // interlaced, with VD pority as negative 0011 0010 1111 1000 0100
VPFE_HD_VD_WID = 0;
VPFE_PIX_LINES = 0x02CF020D;
/*
* sph = 1, nph = 1440, according to page 32-33 of the CCDC spec
* for BT.656 mode, this setting captures only the 720x480 of the
* active NTSV video window
*/
VPFE_HORZ_INFO = width << 1; // Horizontal lines
VPFE_HSIZE_OFF = width << 1; // Horizontal line offset
VPFE_VERT_START = 0; // Vertical start line
VPFE_VERT_LINES = height >> 1; // Vertical lines
VPFE_CULLING = 0xFFFF00FF; // Disable cullng
/*
* Interleave the two fields
*/ // FIINV FOFST LOFTS0 LOFTS1 LOFTS2
VPFE_SDOFST = 0x00000249; // 0 000 001 001 001 001
VPFE_SDR_ADDR = buffer;
VPFE_CLAMP = 0;
VPFE_DCSUB = 0;
VPFE_COLPTN = 0xEE44EE44;
VPFE_BLKCMP = 0;
VPFE_FPC_ADDR = 0x86800000;
VPFE_FPC = 0;
VPFE_VDINT = 0;
VPFE_ALAW = 0;
VPFE_REC656IF = 0x00000003;
/*
* Input format is Cb:Y:Cr:Y, w/ Y in odd-pixel position
*/
VPFE_CCDCFG = 0x00000800;
VPFE_FMTCFG = 0;
VPFE_FMT_HORZ = 0x000002D0;
VPFE_FMT_VERT = 0x0000020E;
VPFE_FMT_ADDR0 = 0;
VPFE_FMT_ADDR1 = 0;
VPFE_FMT_ADDR2 = 0;
VPFE_FMT_ADDR3 = 0;
VPFE_FMT_ADDR4 = 0;
VPFE_FMT_ADDR5 = 0;
VPFE_FMT_ADDR6 = 0;
VPFE_FMT_ADDR7 = 0;
VPFE_PRGEVEN_0 = 0;
VPFE_PRGEVEN_1 = 0;
VPFE_PRGODD_0 = 0;
VPFE_PRGODD_1 = 0;
VPFE_VP_OUT = 0x041A2D00;
VPFE_PCR = 0x00000001; // Enable CCDC
}
/* ------------------------------------------------------------------------ *
* *
* vpbe_init( ) *
* *
* NTSC: *
* Width: 720 *
* Height: 480 *
* *
* *
* ------------------------------------------------------------------------ */
void vpbe_init( Uint32 buffer, Uint32 width, Uint32 height, Uint32 cb_enable )
{
/*
* Setup VPBE
*/
VPSS_CLK_CTRL = 0x00000018; // Enable DAC and VENC clock, both at 27 MHz
VPBE_PCR = 0; // No clock div, clock enable
/*
* Setup OSD
*/
OSD_MODE = 0x000000fc; // Blackground color blue using clut in ROM0
OSD_OSDWIN0MD = 0; // Disable both osd windows and cursor window
OSD_OSDWIN1MD = 0;
OSD_RECTCUR = 0;
OSD_VIDWIN0OFST = width >> 4;
OSD_VIDWIN0ADR = buffer;
OSD_BASEPX = BASEP_X;
OSD_BASEPY = BASEP_Y;
OSD_VIDWIN0XP = 0;
OSD_VIDWIN0YP = 0;
OSD_VIDWIN0XL = width;
OSD_VIDWIN0YL = height >> 1;
OSD_MISCCTL = 0;
OSD_VIDWINMD = 0x00000003; // Disable vwindow 1 and enable vwindow 0
// Frame mode with no up-scaling
/*
* Setup VENC
*/
VENC_VMOD = 0x00000003; // Standard NTSC interlaced output
VENC_VDPRO = cb_enable << 8;
VENC_DACTST = 0;
VENC_DACSEL = 0x00004210;
}
/* ------------------------------------------------------------------------ *
* *
* vpbe_CCD_raw_data( ) *
* *
* NTSC: *
* Width: 720 *
* Height: 480 *
* *
* *
* ------------------------------------------------------------------------ */
void copy_data(Uint32 add_source, Uint32 add_destination, Uint32 length )
{
Uint32 i=1;
for (i=1;i<length;i++)
{
*( volatile Uint32* )add_destination=*( volatile Uint32* )add_source;
add_destination=add_destination+4;
add_source=add_source+4;
}
}
void DDR_capture(Uint32 buffer1, Uint32 buffer2, Uint32 len )
{
Uint32 ii=1;
Uint32 temp1;
Uint32 temp2;
for (ii=1; ii<100;ii++)
{
temp1=buffer1;
temp2=buffer2;
// memcpy(temp1,temp2, len);
//copy_data(temp1,temp2, len);
//DAVINCIEVM_waitusec( 100 );
emif_SDRAM_tranfer (&temp1,&temp2,len);
}
}
Int16 video_loopback_test( )
{
//
CSL_EmifObj emifObj;
CSL_Status status;
CSL_EmifSdramConfig sdramConfig;
CSL_EmifSdramRefreshControl refreshControl;
CSL_EmifSdramTiming timing;
/* Setup The default values to EMIF hardware setup */
CSL_EmifHwSetup hwSetup = CSL_EMIF_HWSETUP_DEFAULTS;
/* SDRAM configurations set as
* selfrefresh rate.................1
* pagesize ........................1
* external banck setup.............1
* CAS latency......................CAS_LATENCY
* bit 13 ..........................1
* EMIF data width .................16bit
* number of internal SDRAM banks ..INT_BANKS
* refresh rate ....................REF_RATE
* timing tras .....................0.
*/
sdramConfig.selfRefresh = 1;
sdramConfig.pageSize = 1;
sdramConfig.extBank = 1;
sdramConfig.casLatency = CAS_LATENCY;
sdramConfig.bit13Enable = 1;
sdramConfig.narrowMode = 1;
sdramConfig.intBank = INT_BANKS;
refreshControl.refreshRate = REF_RATE;
timing.tras = 0;
hwSetup.sdramBankConfig = sdramConfig;
hwSetup.sdramTiming = timing;
hwSetup.emifSdramRefreshControl = refreshControl;
/* EMIF initialization */
status = CSL_emifInit(NULL);
if (status != CSL_SOK) {
printf ("EMIF: Initialization... Failed.\n");
printf ("\tReason: CSL_emifInit failed [Status: 0x%X Handle: 0x%X]\n",
status, hEmif);
emifExampleFailed++;
}
else {
printf ("EMIF: Initialization... Passed.\n");
}
/* Opening the instance */
hEmif = CSL_emifOpen (&emifObj, CSL_EMIF, NULL, &status);
if (status != CSL_SOK || hEmif== NULL) {
printf ("EMIF: Open... Failed.\n");
printf ("\tReason: CSL_emifOpen failed [Status: %d] \n ", status);
emifExampleFailed++;
}
else {
printf ("EMIF: Open... Passed.\n");
}
/* EMIF Hardware setup with required hwSetup values */
status = CSL_emifHwSetup(hEmif, &hwSetup);
if (status != CSL_SOK) {
printf ("EMIF: hardware setup... Failed.\n");
printf ("\tReason: Setup failed [Status: %d] \n ", status);
emifExampleFailed++;
}
else {
printf ("EMIF: HW Setup test... Passed.\n");
}
///////////////////
tvp5146_init( );
vpfe_init( 0x81000000, 720, 480 ); // Setup Front-End
vpbe_init( 0x81000000, 720, 480, 0 ); // Setup Back-End
// DDR_capture(0x81000000, 0x82000000, 0xa9740); //capture
// vpbe_init( 0x81000000, 720, 480, 0 );
//
CSL_emifClose(hEmif);
return 0;
}
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