📄 davincievm.h
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#define VENC_BRTW *( volatile Uint32* )( VENC_BASE + 0x054 )
#define VENC_ACCTL *( volatile Uint32* )( VENC_BASE + 0x058 )
#define VENC_PWMP *( volatile Uint32* )( VENC_BASE + 0x05C )
#define VENC_PWMW *( volatile Uint32* )( VENC_BASE + 0x060 )
#define VENC_DCLKCTL *( volatile Uint32* )( VENC_BASE + 0x064 )
#define VENC_DCLKPTN0 *( volatile Uint32* )( VENC_BASE + 0x068 )
#define VENC_DCLKPTN1 *( volatile Uint32* )( VENC_BASE + 0x06C )
#define VENC_DCLKPTN2 *( volatile Uint32* )( VENC_BASE + 0x070 )
#define VENC_DCLKPTN3 *( volatile Uint32* )( VENC_BASE + 0x074 )
#define VENC_DCLKPTN0A *( volatile Uint32* )( VENC_BASE + 0x078 )
#define VENC_DCLKPTN1A *( volatile Uint32* )( VENC_BASE + 0x07C )
#define VENC_DCLKPTN2A *( volatile Uint32* )( VENC_BASE + 0x080 )
#define VENC_DCLKPTN3A *( volatile Uint32* )( VENC_BASE + 0x084 )
#define VENC_DCLKHS *( volatile Uint32* )( VENC_BASE + 0x088 )
#define VENC_DCLKHSA *( volatile Uint32* )( VENC_BASE + 0x08C )
#define VENC_DCLKHR *( volatile Uint32* )( VENC_BASE + 0x090 )
#define VENC_DCLKVS *( volatile Uint32* )( VENC_BASE + 0x094 )
#define VENC_DCLKVR *( volatile Uint32* )( VENC_BASE + 0x098 )
#define VENC_CAPCTL *( volatile Uint32* )( VENC_BASE + 0x09C )
#define VENC_CAPDO *( volatile Uint32* )( VENC_BASE + 0x0A0 )
#define VENC_CAPDE *( volatile Uint32* )( VENC_BASE + 0x0A4 )
#define VENC_ATR0 *( volatile Uint32* )( VENC_BASE + 0x0A8 )
#define VENC_ATR1 *( volatile Uint32* )( VENC_BASE + 0x0AC )
#define VENC_ATR2 *( volatile Uint32* )( VENC_BASE + 0x0B0 )
#define VENC_EPSON_LCDCTL *( volatile Uint32* )( VENC_BASE + 0x0B4 )
#define VENC_VSTAT *( volatile Uint32* )( VENC_BASE + 0x0B8 )
#define VENC_RAMADR *( volatile Uint32* )( VENC_BASE + 0x0BC )
#define VENC_RAMPORT *( volatile Uint32* )( VENC_BASE + 0x0C0 )
#define VENC_DACTST *( volatile Uint32* )( VENC_BASE + 0x0C4 )
#define VENC_YCOLVL *( volatile Uint32* )( VENC_BASE + 0x0C8 )
#define VENC_SCPROG *( volatile Uint32* )( VENC_BASE + 0x0CC )
#define VENC_CVBS *( volatile Uint32* )( VENC_BASE + 0x0DC )
#define VENC_CMPNT *( volatile Uint32* )( VENC_BASE + 0x0E0 )
#define VENC_ETMG0 *( volatile Uint32* )( VENC_BASE + 0x0E4 )
#define VENC_ETMG1 *( volatile Uint32* )( VENC_BASE + 0x0E8 )
#define VENC_ETMG2 *( volatile Uint32* )( VENC_BASE + 0x0EC )
#define VENC_ETMG3 *( volatile Uint32* )( VENC_BASE + 0x0F0 )
#define VENC_DACSEL *( volatile Uint32* )( VENC_BASE + 0x0F4 )
#define VENC_ARGBX0 *( volatile Uint32* )( VENC_BASE + 0x100 )
#define VENC_ARGBX1 *( volatile Uint32* )( VENC_BASE + 0x104 )
#define VENC_ARGBX2 *( volatile Uint32* )( VENC_BASE + 0x108 )
#define VENC_ARGBX3 *( volatile Uint32* )( VENC_BASE + 0x10C )
#define VENC_ARGBX4 *( volatile Uint32* )( VENC_BASE + 0x110 )
#define VENC_DRGBX0 *( volatile Uint32* )( VENC_BASE + 0x114 )
#define VENC_DRGBX1 *( volatile Uint32* )( VENC_BASE + 0x118 )
#define VENC_DRGBX2 *( volatile Uint32* )( VENC_BASE + 0x11C )
#define VENC_DRGBX3 *( volatile Uint32* )( VENC_BASE + 0x120 )
#define VENC_DRGBX4 *( volatile Uint32* )( VENC_BASE + 0x124 )
#define VENC_VSTARTA *( volatile Uint32* )( VENC_BASE + 0x128 )
#define VENC_OSDCLK0 *( volatile Uint32* )( VENC_BASE + 0x12C )
#define VENC_OSDCLK1 *( volatile Uint32* )( VENC_BASE + 0x130 )
#define VENC_HVLDCL0 *( volatile Uint32* )( VENC_BASE + 0x134 )
#define VENC_HVLDCL1 *( volatile Uint32* )( VENC_BASE + 0x138 )
#define VENC_OSDHADV *( volatile Uint32* )( VENC_BASE + 0x13C )
#define VENC_SCTEST0 *( volatile Uint32* )( VENC_BASE + 0x140 )
#define VENC_SCTEST1 *( volatile Uint32* )( VENC_BASE + 0x144 )
#define VENC_SCTEST2 *( volatile Uint32* )( VENC_BASE + 0x148 )
#define VENC_VTEST0 *( volatile Uint32* )( VENC_BASE + 0x14C )
#define VENC_VTEST1 *( volatile Uint32* )( VENC_BASE + 0x150 )
#define VENC_VTEST2 *( volatile Uint32* )( VENC_BASE + 0x154 )
/* ------------------------------------------------------------------------ *
* *
* OSD Control *
* *
* ------------------------------------------------------------------------ */
#define OSD_BASE 0x01c72600
#define OSD_MODE *( volatile Uint32* )( OSD_BASE + 0x00 )
#define OSD_VIDWINMD *( volatile Uint32* )( OSD_BASE + 0x04 )
#define OSD_OSDWIN0MD *( volatile Uint32* )( OSD_BASE + 0x08 )
#define OSD_OSDWIN1MD *( volatile Uint32* )( OSD_BASE + 0x0C )
#define OSD_RECTCUR *( volatile Uint32* )( OSD_BASE + 0x10 )
#define OSD_VIDWIN0OFST *( volatile Uint32* )( OSD_BASE + 0x18 )
#define OSD_VIDWIN1OFST *( volatile Uint32* )( OSD_BASE + 0x1C )
#define OSD_OSDWIN0OFST *( volatile Uint32* )( OSD_BASE + 0x20 )
#define OSD_OSDWIN1OFST *( volatile Uint32* )( OSD_BASE + 0x24 )
#define OSD_VIDWIN0ADR *( volatile Uint32* )( OSD_BASE + 0x2C )
#define OSD_VIDWIN1ADR *( volatile Uint32* )( OSD_BASE + 0x30 )
#define OSD_OSDWIN0ADR *( volatile Uint32* )( OSD_BASE + 0x38 )
#define OSD_OSDWIN1ADR *( volatile Uint32* )( OSD_BASE + 0x3C )
#define OSD_BASEPX *( volatile Uint32* )( OSD_BASE + 0x40 )
#define OSD_BASEPY *( volatile Uint32* )( OSD_BASE + 0x44 )
#define OSD_VIDWIN0XP *( volatile Uint32* )( OSD_BASE + 0x48 )
#define OSD_VIDWIN0YP *( volatile Uint32* )( OSD_BASE + 0x4C )
#define OSD_VIDWIN0XL *( volatile Uint32* )( OSD_BASE + 0x50 )
#define OSD_VIDWIN0YL *( volatile Uint32* )( OSD_BASE + 0x54 )
#define OSD_VIDWIN1XP *( volatile Uint32* )( OSD_BASE + 0x58 )
#define OSD_VIDWIN1YP *( volatile Uint32* )( OSD_BASE + 0x5C )
#define OSD_VIDWIN1XL *( volatile Uint32* )( OSD_BASE + 0x60 )
#define OSD_VIDWIN1YL *( volatile Uint32* )( OSD_BASE + 0x64 )
#define OSD_OSDWIN0XP *( volatile Uint32* )( OSD_BASE + 0x68 )
#define OSD_OSDWIN0YP *( volatile Uint32* )( OSD_BASE + 0x6C )
#define OSD_OSDWIN0XL *( volatile Uint32* )( OSD_BASE + 0x70 )
#define OSD_OSDWIN0YL *( volatile Uint32* )( OSD_BASE + 0x74 )
#define OSD_OSDWIN1XP *( volatile Uint32* )( OSD_BASE + 0x78 )
#define OSD_OSDWIN1YP *( volatile Uint32* )( OSD_BASE + 0x7C )
#define OSD_OSDWIN1XL *( volatile Uint32* )( OSD_BASE + 0x80 )
#define OSD_OSDWIN1YL *( volatile Uint32* )( OSD_BASE + 0x84 )
#define OSD_CURXP *( volatile Uint32* )( OSD_BASE + 0x88 )
#define OSD_CURYP *( volatile Uint32* )( OSD_BASE + 0x8C )
#define OSD_CURXL *( volatile Uint32* )( OSD_BASE + 0x90 )
#define OSD_CURYL *( volatile Uint32* )( OSD_BASE + 0x94 )
#define OSD_W0BMP01 *( volatile Uint32* )( OSD_BASE + 0xA0 )
#define OSD_W0BMP23 *( volatile Uint32* )( OSD_BASE + 0xA4 )
#define OSD_W0BMP45 *( volatile Uint32* )( OSD_BASE + 0xA8 )
#define OSD_W0BMP67 *( volatile Uint32* )( OSD_BASE + 0xAC )
#define OSD_W0BMP89 *( volatile Uint32* )( OSD_BASE + 0xB0 )
#define OSD_W0BMPAB *( volatile Uint32* )( OSD_BASE + 0xB4 )
#define OSD_W0BMPCD *( volatile Uint32* )( OSD_BASE + 0xB8 )
#define OSD_W0BMPEF *( volatile Uint32* )( OSD_BASE + 0xBC )
#define OSD_W1BMP01 *( volatile Uint32* )( OSD_BASE + 0xC0 )
#define OSD_W1BMP23 *( volatile Uint32* )( OSD_BASE + 0xC4 )
#define OSD_W1BMP45 *( volatile Uint32* )( OSD_BASE + 0xC8 )
#define OSD_W1BMP67 *( volatile Uint32* )( OSD_BASE + 0xCC )
#define OSD_W1BMP89 *( volatile Uint32* )( OSD_BASE + 0xD0 )
#define OSD_W1BMPAB *( volatile Uint32* )( OSD_BASE + 0xD4 )
#define OSD_W1BMPCD *( volatile Uint32* )( OSD_BASE + 0xD8 )
#define OSD_W1BMPEF *( volatile Uint32* )( OSD_BASE + 0xDC )
#define OSD_TI_TEST *( volatile Uint32* )( OSD_BASE + 0xE0 )
#define OSD_MISCCTL *( volatile Uint32* )( OSD_BASE + 0xE8 )
#define OSD_CLUTRAMYCB *( volatile Uint32* )( OSD_BASE + 0xEC )
#define OSD_CLUTRAMCR *( volatile Uint32* )( OSD_BASE + 0xF0 )
#define OSD_TRANSPVAL *( volatile Uint32* )( OSD_BASE + 0xF0 )
#define OSD_PPVWIN0ADR *( volatile Uint32* )( OSD_BASE + 0xFC )
/* ------------------------------------------------------------------------ *
* *
* VPBE Control *
* *
* ------------------------------------------------------------------------ */
#define VPBE_BASE 0x01c72780
#define VPBE_PID *( volatile Uint32* )( VPBE_BASE + 0x00 )
#define VPBE_PCR *( volatile Uint32* )( VPBE_BASE + 0x04 )
/* ------------------------------------------------------------------------ *
* *
* AEMIF Controller *
* *
* ------------------------------------------------------------------------ */
#define AEMIF_BASE 0x01E00000
#define AEMIF_RCSR *( volatile Uint32* )( AEMIF_BASE + 0x00 )
#define AEMIF_WAITCFG *( volatile Uint32* )( AEMIF_BASE + 0x04 )
#define AEMIF_ACFG2 *( volatile Uint32* )( AEMIF_BASE + 0x10 )
#define AEMIF_ACFG3 *( volatile Uint32* )( AEMIF_BASE + 0x14 )
#define AEMIF_ACFG4 *( volatile Uint32* )( AEMIF_BASE + 0x18 )
#define AEMIF_ACFG5 *( volatile Uint32* )( AEMIF_BASE + 0x1C )
#define AEMIF_AINTRAW *( volatile Uint32* )( AEMIF_BASE + 0x40 )
#define AEMIF_AINTMASK *( volatile Uint32* )( AEMIF_BASE + 0x44 )
#define AEMIF_AINTMASKSET *( volatile Uint32* )( AEMIF_BASE + 0x48 )
#define AEMIF_INTMASKCLEAR *( volatile Uint32* )( AEMIF_BASE + 0x4C )
#define AEMIF_NANDFCR *( volatile Uint32* )( AEMIF_BASE + 0x60 )
#define AEMIF_NANDSTAT *( volatile Uint32* )( AEMIF_BASE + 0x64 )
#define AEMIF_NANDECC2 *( volatile Uint32* )( AEMIF_BASE + 0x70 )
#define AEMIF_NANDECC3 *( volatile Uint32* )( AEMIF_BASE + 0x74 )
#define AEMIF_NANDECC4 *( volatile Uint32* )( AEMIF_BASE + 0x78 )
#define AEMIF_NANDECC5 *( volatile Uint32* )( AEMIF_BASE + 0x7C )
#define AEMIF_MAX_TIMEOUT_16BIT 0x3FFFFFFD
/* ------------------------------------------------------------------------ *
* *
* DDR Controller *
* *
* ------------------------------------------------------------------------ */
#define DDR_BASE 0x20000000
#define EIDRR *( volatile Uint32* )( DDR_BASE + 0x00 ) // EMIF Module ID and Revision Register
#define SDSTAT *( volatile Uint32* )( DDR_BASE + 0x04 ) // SDRAM Status Register
#define SDCFG *( volatile Uint32* )( DDR_BASE + 0x08 ) // SDRAM Bank Config Register
#define SDREF *( volatile Uint32* )( DDR_BASE + 0x0C ) // SDRAM Refresh Control Register
#define SDTIM0 *( volatile Uint32* )( DDR_BASE + 0x10 ) // SDRAM Timing Register
#define SDTIM1 *( volatile Uint32* )( DDR_BASE + 0x14 ) // SDRAM Timing Register
#define VBUSP *( volatile Uint32* )( DDR_BASE + 0x20 ) // VBUSM Burst Priority Register
#define PERFCNT1 *( volatile Uint32* )( DDR_BASE + 0x40 ) // Performance Counter Register 1
#define PERFCNT2 *( volatile Uint32* )( DDR_BASE + 0x44 ) // Performance Counter Register 2
#define PERFCNTCFG *( volatile Uint32* )( DDR_BASE + 0x48 ) // Performance Counter Config Register
#define PERFCNTMSTREGSEL *( volatile Uint32* )( DDR_BASE + 0x4C ) // Performance Counter Master Region Select Register
#define INTRAW *( volatile Uint32* )( DDR_BASE + 0xC0 ) // Interrupt Raw Register
#define INTMASK *( volatile Uint32* )( DDR_BASE + 0xC4 ) // Interrupt Masked Register
#define INTMASKSET *( volatile Uint32* )( DDR_BASE + 0xC8 ) // Interrupt Mask Set Register
#define INTMASKCLR *( volatile Uint32* )( DDR_BASE + 0xCC ) // Interrupt Mask Clear Register
#define DDRPHYREV *( volatile Uint32* )( DDR_BASE + 0xE0 ) // DDR PHY ID and Revision Register
#define DDRCTL *( volatile Uint32* )( DDR_BASE + 0xE4 ) // DDR PHY Control Register
#define PHYSTAT *( volatile Uint32* )( DDR_BASE + 0xE8 ) // DDR PHY Status Register
/* ------------------------------------------------------------------------ *
* *
* Prototypes *
* *
* ------------------------------------------------------------------------ */
Int16 DAVINCIEVM_init( );
void DAVINCIEVM_wait( Uint32 delay );
void DAVINCIEVM_waitusec( Uint32 usec );
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