usbslavecontrolbi.v

对usb设备控制的ip核进行了重新设计并进一步优化

          EP3IsoEn <= dataIn[`ENDPOINT_ISO_ENABLE_BIT];
          EP3SendStall <= dataIn[`ENDPOINT_SEND_STALL_BIT];
          EP3DataSequence <= dataIn[`ENDPOINT_OUTDATA_SEQUENCE_BIT];
          EP3SetReady <= dataIn[`ENDPOINT_READY_BIT];
          EP3Enable <= dataIn[`ENDPOINT_ENABLE_BIT];
        end
        `SC_CONTROL_REG : SCControlReg <= dataIn[6:0];
        `SC_ADDRESS : SCAddrReg <= dataIn[6:0];
        `SC_INTERRUPT_STATUS_REG : begin
          clrVBusDetReq <= dataIn[`VBUS_DET_INT_BIT];
          clrNAKReq <= dataIn[`NAK_SENT_INT_BIT];
          clrSOFReq <= dataIn[`SOF_RECEIVED_BIT];
          clrResetReq <= dataIn[`RESET_EVENT_BIT];
          clrResInReq <= dataIn[`RESUME_INT_BIT];
          clrTransDoneReq <= dataIn[`TRANS_DONE_BIT];
        end
        `SC_INTERRUPT_MASK_REG  : interruptMaskReg <= dataIn[5:0];
      endcase
    end
  end
end

//interrupt control 
always @(posedge busClk)
begin
  if (rstSyncToBusClk == 1'b1) begin
    vBusDetInt <= 1'b0;
    NAKSentInt <= 1'b0;
    SOFRxedInt <= 1'b0;
    resetEventInt <= 1'b0;
    resumeInt <= 1'b0;
    transDoneInt <= 1'b0;
  end
  else begin
    if (vBusDetectInSTB[0] != vBusDetectInSTB[1])
      vBusDetInt <= 1'b1;
    else if (clrVBusDetReq == 1'b1)
      vBusDetInt <= 1'b0; 

    if (NAKSentInSTB[1] == 1'b1 && NAKSentInSTB[0] == 1'b0)
      NAKSentInt <= 1'b1;
    else if (clrNAKReq == 1'b1)
      NAKSentInt <= 1'b0; 
    
    if (SOFRxedInSTB[1] == 1'b1 && SOFRxedInSTB[0] == 1'b0)
      SOFRxedInt <= 1'b1;
    else if (clrSOFReq == 1'b1)
      SOFRxedInt <= 1'b0;
    
    if (resetEventInSTB[1] == 1'b1 && resetEventInSTB[0] == 1'b0)
      resetEventInt <= 1'b1;
    else if (clrResetReq == 1'b1)
      resetEventInt <= 1'b0;
    
    if (resumeIntInSTB[1] == 1'b1 && resumeIntInSTB[0] == 1'b0)
      resumeInt <= 1'b1;
    else if (clrResInReq == 1'b1)
      resumeInt <= 1'b0;

    if (transDoneInSTB[1] == 1'b1 && transDoneInSTB[0] == 1'b0)
      transDoneInt <= 1'b1;
    else if (clrTransDoneReq == 1'b1)
      transDoneInt <= 1'b0;
  end
end

//mask interrupts
always @(*) begin
  transDoneIntOut <= transDoneInt & interruptMaskReg[`TRANS_DONE_BIT];
  resumeIntOut <= resumeInt & interruptMaskReg[`RESUME_INT_BIT];
  resetEventIntOut <= resetEventInt & interruptMaskReg[`RESET_EVENT_BIT];
  SOFRxedIntOut <= SOFRxedInt & interruptMaskReg[`SOF_RECEIVED_BIT];
  NAKSentIntOut <= NAKSentInt & interruptMaskReg[`NAK_SENT_INT_BIT];
  vBusDetIntOut <= vBusDetInt & interruptMaskReg[`VBUS_DET_INT_BIT];
end  

//end point ready, set/clear
//Since 'busClk' can be a higher freq than 'usbClk',
//'EP0SetReady' etc must be delayed with respect to other control signals, thus
//ensuring that control signals have been clocked through to 'usbClk' clock
//domain before the ready is asserted.
//Not sure this is required because there is at least two 'usbClk' ticks between
//detection of 'EP0Ready' and sampling of related control signals.
always @(posedge busClk)
begin
  if (rstSyncToBusClk == 1'b1) begin
    EP0Ready <= 1'b0;
    EP1Ready <= 1'b0;
    EP2Ready <= 1'b0;
    EP3Ready <= 1'b0;
  end
  else begin
    if (EP0SetReady == 1'b1)
      EP0Ready <= 1'b1;
    else if (clrEP0ReadySTB[1] == 1'b1 && clrEP0ReadySTB[0] == 1'b0)
      EP0Ready <= 1'b0;
    
    if (EP1SetReady == 1'b1)
      EP1Ready <= 1'b1;
    else if (clrEP1ReadySTB[1] == 1'b1 && clrEP1ReadySTB[0] == 1'b0)
      EP1Ready <= 1'b0;
    
    if (EP2SetReady == 1'b1)
      EP2Ready <= 1'b1;
    else if (clrEP2ReadySTB[1] == 1'b1 && clrEP2ReadySTB[0] == 1'b0)
      EP2Ready <= 1'b0;
    
    if (EP3SetReady == 1'b1)
      EP3Ready <= 1'b1;
    else if (clrEP3ReadySTB[1] == 1'b1 && clrEP3ReadySTB[0] == 1'b0)
      EP3Ready <= 1'b0;
  end
end  
  
//break out control signals
always @(SCControlReg) begin
  SCGlobalEnSTB <= SCControlReg[`SC_GLOBAL_ENABLE_BIT];
  TxLineStateSTB <= SCControlReg[`SC_TX_LINE_STATE_MSBIT:`SC_TX_LINE_STATE_LSBIT];
  LineDirectControlEnSTB <= SCControlReg[`SC_DIRECT_CONTROL_BIT];
  fullSpeedPolSTB <= SCControlReg[`SC_FULL_SPEED_LINE_POLARITY_BIT]; 
  fullSpeedRateSTB <= SCControlReg[`SC_FULL_SPEED_LINE_RATE_BIT];
  connectSlaveToHostSTB <= SCControlReg[`SC_CONNECT_TO_HOST_BIT];
end

//combine endpoint control signals 
always @(*) 
begin
  endP0ControlRegSTB <= {EP0IsoEn, EP0SendStall, EP0DataSequence, EP0Ready, EP0Enable};
  endP1ControlRegSTB <= {EP1IsoEn, EP1SendStall, EP1DataSequence, EP1Ready, EP1Enable};
  endP2ControlRegSTB <= {EP2IsoEn, EP2SendStall, EP2DataSequence, EP2Ready, EP2Enable};
  endP3ControlRegSTB <= {EP3IsoEn, EP3SendStall, EP3DataSequence, EP3Ready, EP3Enable};
end
      
      
// async read mux
always @(*)
begin
  case (address)
      `EP0_CTRL_REG : dataOut <= endP0ControlRegSTB;
      `EP0_STS_REG : dataOut <= EP0StatusRegSTB;
      `EP0_TRAN_TYPE_STS_REG : dataOut <= endP0TransTypeRegSTB;
      `EP0_NAK_TRAN_TYPE_STS_REG : dataOut <= endP0NAKTransTypeRegSTB;
      `EP1_CTRL_REG : dataOut <= endP1ControlRegSTB;
      `EP1_STS_REG :  dataOut <= EP1StatusRegSTB;
      `EP1_TRAN_TYPE_STS_REG : dataOut <= endP1TransTypeRegSTB;
      `EP1_NAK_TRAN_TYPE_STS_REG : dataOut <= endP1NAKTransTypeRegSTB;
      `EP2_CTRL_REG : dataOut <= endP2ControlRegSTB;
      `EP2_STS_REG :  dataOut <= EP2StatusRegSTB;
      `EP2_TRAN_TYPE_STS_REG : dataOut <= endP2TransTypeRegSTB;
      `EP2_NAK_TRAN_TYPE_STS_REG : dataOut <= endP2NAKTransTypeRegSTB;
      `EP3_CTRL_REG : dataOut <= endP3ControlRegSTB;
      `EP3_STS_REG :  dataOut <= EP3StatusRegSTB;
      `EP3_TRAN_TYPE_STS_REG : dataOut <= endP3TransTypeRegSTB;
      `EP3_NAK_TRAN_TYPE_STS_REG : dataOut <= endP3NAKTransTypeRegSTB;
      `SC_CONTROL_REG : dataOut <= SCControlReg;
      `SC_LINE_STATUS_REG : dataOut <= {5'b00000, vBusDetectInSTB[0], connectStateInSTB}; 
      `SC_INTERRUPT_STATUS_REG :  dataOut <= {2'b00, vBusDetInt, NAKSentInt, SOFRxedInt, resetEventInt, resumeInt, transDoneInt};
      `SC_INTERRUPT_MASK_REG  : dataOut <= {2'b00, interruptMaskReg};
      `SC_ADDRESS : dataOut <= {1'b0, SCAddrReg};
      `SC_FRAME_NUM_MSP : dataOut <= {5'b00000, frameNumSTB[10:8]};
      `SC_FRAME_NUM_LSP : dataOut <= frameNumSTB[7:0];
      default: dataOut <= 8'h00;
  endcase
end


//Extend SOFRxedIn, resetEventIn, resumeIntIn, transDoneIn, NAKSentIn from 1 tick
//pulses to 3 tick pulses
always @(posedge usbClk) begin
  if (rstSyncToUsbClk == 1'b1) begin
    SOFRxedInExtend <= 3'b000;
    resetEventInExtend <= 3'b000;
    resumeIntInExtend <= 3'b000;
    transDoneInExtend <= 3'b000;
    NAKSentInExtend <= 3'b000;
    clrEP0ReadyExtend <= 3'b000;
    clrEP1ReadyExtend <= 3'b000;
    clrEP2ReadyExtend <= 3'b000;
    clrEP3ReadyExtend <= 3'b000;
  end
  else begin
    if (SOFRxedIn == 1'b1)
      SOFRxedInExtend <= 3'b111;
    else
      SOFRxedInExtend <= {1'b0, SOFRxedInExtend[2:1]};
    if (resetEventIn == 1'b1)
      resetEventInExtend <= 3'b111;
    else
      resetEventInExtend <= {1'b0, resetEventInExtend[2:1]};
    if (resumeIntIn == 1'b1)
      resumeIntInExtend <= 3'b111;
    else
      resumeIntInExtend <= {1'b0, resumeIntInExtend[2:1]};
    if (transDoneIn == 1'b1)
      transDoneInExtend <= 3'b111;
    else
      transDoneInExtend <= {1'b0, transDoneInExtend[2:1]};
    if (NAKSentIn == 1'b1)
      NAKSentInExtend <= 3'b111;
    else
      NAKSentInExtend <= {1'b0, NAKSentInExtend[2:1]};
    if (clrEP0Ready == 1'b1)
      clrEP0ReadyExtend <= 3'b111;
    else
      clrEP0ReadyExtend <= {1'b0, clrEP0ReadyExtend[2:1]};
    if (clrEP1Ready == 1'b1)
      clrEP1ReadyExtend <= 3'b111;
    else
      clrEP1ReadyExtend <= {1'b0, clrEP1ReadyExtend[2:1]};
    if (clrEP2Ready == 1'b1)
      clrEP2ReadyExtend <= 3'b111;
    else
      clrEP2ReadyExtend <= {1'b0, clrEP2ReadyExtend[2:1]};
    if (clrEP3Ready == 1'b1)
      clrEP3ReadyExtend <= 3'b111;
    else
      clrEP3ReadyExtend <= {1'b0, clrEP3ReadyExtend[2:1]};
  end
end

//re-sync from busClk to usbClk. 
always @(posedge usbClk) begin
  if (rstSyncToUsbClk == 1'b1) begin
    endP0ControlReg <= {5{1'b0}};
    endP0ControlReg1 <= {5{1'b0}};
    endP1ControlReg <= {5{1'b0}};
    endP1ControlReg1 <= {5{1'b0}};
    endP2ControlReg <= {5{1'b0}};
    endP2ControlReg1 <= {5{1'b0}};
    endP3ControlReg <= {5{1'b0}};
    endP3ControlReg1 <= {5{1'b0}};
    SCGlobalEn <= 1'b0;
    SCGlobalEn_reg1 <= 1'b0;
    TxLineState <= 2'b00;
    TxLineState_reg1 <= 2'b00;
    LineDirectControlEn <= 1'b0;
    LineDirectControlEn_reg1 <= 1'b0;
    fullSpeedPol <= 1'b0;
    fullSpeedPol_reg1 <= 1'b0;
    fullSpeedRate <= 1'b0;
    fullSpeedRate_reg1 <= 1'b0;
    connectSlaveToHost <= 1'b0;
    connectSlaveToHost_reg1 <= 1'b0;
  end
  else begin
    endP0ControlReg1 <= endP0ControlRegSTB;
    endP0ControlReg <= endP0ControlReg1;
    endP1ControlReg1 <= endP1ControlRegSTB;
    endP1ControlReg <= endP1ControlReg1;
    endP2ControlReg1 <= endP2ControlRegSTB;
    endP2ControlReg <= endP2ControlReg1;
    endP3ControlReg1 <= endP3ControlRegSTB;
    endP3ControlReg <= endP3ControlReg1;
    SCGlobalEn_reg1 <= SCGlobalEnSTB;
    SCGlobalEn <= SCGlobalEn_reg1;
    TxLineState_reg1 <= TxLineStateSTB;
    TxLineState <= TxLineState_reg1;
    LineDirectControlEn_reg1 <= LineDirectControlEnSTB;
    LineDirectControlEn <= LineDirectControlEn_reg1;
    fullSpeedPol_reg1 <= fullSpeedPolSTB; 
    fullSpeedPol <= fullSpeedPol_reg1; 
    fullSpeedRate_reg1 <= fullSpeedRateSTB;
    fullSpeedRate <= fullSpeedRate_reg1;
    connectSlaveToHost_reg1 <= connectSlaveToHostSTB;
    connectSlaveToHost <= connectSlaveToHost_reg1;
  end
end

//re-sync from usbClk and async inputs to busClk. Since 'NAKSentIn', 'SOFRxedIn' etc 
//are only asserted for 3 usbClk ticks
//busClk freq must be greater than usbClk/3 (plus some allowance for setup and hold) freq
always @(posedge busClk) begin
  if (rstSyncToBusClk == 1'b1) begin
    vBusDetectInSTB <= 3'b000;
    NAKSentInSTB <= 3'b000;
    SOFRxedInSTB <= 3'b000;
    resetEventInSTB <= 3'b000;
    resumeIntInSTB <= 3'b000;
    transDoneInSTB <= 3'b000;
    clrEP0ReadySTB <= 3'b000;
    clrEP1ReadySTB <= 3'b000;
    clrEP2ReadySTB <= 3'b000;
    clrEP3ReadySTB <= 3'b000;
    EP0StatusRegSTB <= 8'h00;
    EP0StatusRegSTB_reg1 <= 8'h00;
    EP1StatusRegSTB <= 8'h00;
    EP1StatusRegSTB_reg1 <= 8'h00;
    EP2StatusRegSTB <= 8'h00;
    EP2StatusRegSTB_reg1 <= 8'h00;
    EP3StatusRegSTB <= 8'h00;
    EP3StatusRegSTB_reg1 <= 8'h00;
    endP0TransTypeRegSTB <= 2'b00;
    endP0TransTypeRegSTB_reg1 <= 2'b00;
    endP1TransTypeRegSTB <= 2'b00;
    endP1TransTypeRegSTB_reg1 <= 2'b00;
    endP2TransTypeRegSTB <= 2'b00;
    endP2TransTypeRegSTB_reg1 <= 2'b00;
    endP3TransTypeRegSTB <= 2'b00;
    endP3TransTypeRegSTB_reg1 <= 2'b00;
    endP0NAKTransTypeRegSTB <= 2'b00;
    endP0NAKTransTypeRegSTB_reg1 <= 2'b00;
    endP1NAKTransTypeRegSTB <= 2'b00;
    endP1NAKTransTypeRegSTB_reg1 <= 2'b00;
    endP2NAKTransTypeRegSTB <= 2'b00;
    endP2NAKTransTypeRegSTB_reg1 <= 2'b00;
    endP3NAKTransTypeRegSTB <= 2'b00;
    endP3NAKTransTypeRegSTB_reg1 <= 2'b00;
    frameNumSTB <= {11{1'b0}};
    frameNumSTB_reg1 <= {11{1'b0}};
    connectStateInSTB <= 2'b00;
    connectStateInSTB_reg1 <= 2'b00;
  end
  else begin
    vBusDetectInSTB <= {vBusDetectIn, vBusDetectInSTB[2:1]};
    NAKSentInSTB <= {NAKSentInExtend[0], NAKSentInSTB[2:1]};
    SOFRxedInSTB <= {SOFRxedInExtend[0], SOFRxedInSTB[2:1]};
    resetEventInSTB <= {resetEventInExtend[0], resetEventInSTB[2:1]};
    resumeIntInSTB <= {resumeIntInExtend[0], resumeIntInSTB[2:1]};
    transDoneInSTB <= {transDoneInExtend[0], transDoneInSTB[2:1]};
    clrEP0ReadySTB <= {clrEP0ReadyExtend[0], clrEP0ReadySTB[2:1]};
    clrEP1ReadySTB <= {clrEP1ReadyExtend[0], clrEP1ReadySTB[2:1]};
    clrEP2ReadySTB <= {clrEP2ReadyExtend[0], clrEP2ReadySTB[2:1]};
    clrEP3ReadySTB <= {clrEP3ReadyExtend[0], clrEP3ReadySTB[2:1]};
    EP0StatusRegSTB_reg1 <= EP0StatusReg;
    EP0StatusRegSTB <= EP0StatusRegSTB_reg1;
    EP1StatusRegSTB_reg1 <= EP1StatusReg;
    EP1StatusRegSTB <= EP1StatusRegSTB_reg1;
    EP2StatusRegSTB_reg1 <= EP2StatusReg;
    EP2StatusRegSTB <= EP2StatusRegSTB_reg1;
    EP3StatusRegSTB_reg1 <= EP3StatusReg;
    EP3StatusRegSTB <= EP3StatusRegSTB_reg1;
    endP0TransTypeRegSTB_reg1 <= endP0TransTypeReg;
    endP0TransTypeRegSTB <= endP0TransTypeRegSTB_reg1;
    endP1TransTypeRegSTB_reg1 <= endP1TransTypeReg;
    endP1TransTypeRegSTB <= endP1TransTypeRegSTB_reg1;
    endP2TransTypeRegSTB_reg1 <= endP2TransTypeReg;
    endP2TransTypeRegSTB <= endP2TransTypeRegSTB_reg1;
    endP3TransTypeRegSTB_reg1 <= endP3TransTypeReg;
    endP3TransTypeRegSTB <= endP3TransTypeRegSTB_reg1;
    endP0NAKTransTypeRegSTB_reg1 <= endP0NAKTransTypeReg;
    endP0NAKTransTypeRegSTB <= endP0NAKTransTypeRegSTB_reg1;
    endP1NAKTransTypeRegSTB_reg1 <= endP1NAKTransTypeReg;
    endP1NAKTransTypeRegSTB <= endP1NAKTransTypeRegSTB_reg1;
    endP2NAKTransTypeRegSTB_reg1 <= endP2NAKTransTypeReg;
    endP2NAKTransTypeRegSTB <= endP2NAKTransTypeRegSTB_reg1;
    endP3NAKTransTypeRegSTB_reg1 <= endP3NAKTransTypeReg;
    endP3NAKTransTypeRegSTB <= endP3NAKTransTypeRegSTB_reg1;
    frameNumSTB_reg1 <= frameNum;
    frameNumSTB <= frameNumSTB_reg1;
    connectStateInSTB_reg1 <= connectStateIn;
    connectStateInSTB <= connectStateInSTB_reg1;
  end
end


endmodule