processrxbyte.asf

对usb设备控制的ip核进行了重新设计并进一步优化

VERSION=1.21
HEADER
FILE="processRxByte.asf"
FID=4094ffa4
LANGUAGE=VERILOG
ENTITY="processRxByte"
FREEOID=384
"LIBRARIES=//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// processRxByte\n////                                                              ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/                 ////\n////                                                              ////\n//// Module Description:                                          ////\n//// \n////                                                              ////\n//// To Do:                                                       ////\n//// \n////                                                              ////\n//// Author(s):                                                   ////\n//// - Steve Fielding, [e-mail]                 ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////\n////                                                              ////\n//// This source file may be used and distributed without         ////\n//// restriction provided that this copyright statement is not    ////\n//// removed from the file and that any derivative work contains  ////\n//// the original copyright notice and the associated disclaimer. ////\n////                                                              ////\n//// This source file is free software; you can redistribute it   ////\n//// and/or modify it under the terms of the GNU Lesser General   ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any   ////\n//// later version.                                               ////\n////                                                              ////\n//// This source is distributed in the hope that it will be       ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////\n//// PURPOSE. See the GNU Lesser General Public License for more  ////\n//// details.                                                     ////\n////                                                              ////\n//// You should have received a copy of the GNU Lesser General    ////\n//// Public License along with this source; if not, download it   ////\n//// from http://www.opencores.org/lgpl.shtml                     ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n//\n`include \"timescale.v\"\n`include \"usbSerialInterfaceEngine_h.v\"\n`include \"usbConstants_h.v\"\n"
MULTIPLEARCHSTATUS=FALSE
SYNTHESISATTRIBUTES=TRUE
HEADER_PARAM="AUTHOR,"
HEADER_PARAM="COMPANY,"
HEADER_PARAM="CREATIONDATE,"
HEADER_PARAM="TITLE,No Title"
BLOCKTABLE_FILE=""
BLOCKTABLE_TEMPL="0"
BLOCKTABLE_VISIBLE="1"
END
BUNDLES
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B T "Actions" 0,0,0 0 0 1 255,255,255 0 3333 0 0000 0 "Arial" 0
B T "Labels" 0,0,0 0 0 0 0,0,0 0 3333 0 0000 0 "Arial" 0
B L "Transitions" 0,0,0 0 0 1 0,0,0 1 3527 1480 0000 0 "Arial" 0
B F "Ports" 0,0,0 0 0 1 0,255,255 1 3527 1480 0000 0 "Arial" 0
B L "Errors" 255,0,0 0 3 1 255,255,255 1 3527 1480 0000 0 "Arial" 0
B T "State Labels" 0,0,0 0 0 0 0,0,0 0 3333 0 0000 0 "Arial" 4
B F "Current State" 255,255,0 0 0 1 255,255,0 1 3527 1480 0000 0 "Arial" 0
B T "Comments" 157,157,157 0 0 1 255,255,255 0 3333 0 0000 0 "Arial" 0
B L "Info" 0,255,0 0 3 1 255,255,255 1 3527 1480 0000 0 "Arial" 0
B F "Junction" 0,0,0 0 0 1 255,0,0 1 3527 1480 0000 0 "Arial" 0
B F "Initial State Indicator" 0,0,0 0 0 1 240,140,40 1 3527 1480 0000 0 "Arial" 0
B T "Alias" 0,128,0 0 0 1 255,255,255 0 3527 1480 0000 0 "Arial" 0
B F "Delay" 0,0,0 0 0 1 180,180,180 1 3527 1480 0000 0 "Arial" 0
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OBJECTS
L 15 16 0 TEXT "State Labels" | 115714,112364 1 0 0 "CHK_PID"
W 13 6 0 12 9 BEZIER "Transitions" | 22016,192062 26512,191798 31110,187768 35074,185908
I 12 6 0 Builtin Reset | 22016,192062
S 11 6 0 ELLIPSE "States" | 41526,162904 6500 6500
L 10 11 0 TEXT "State Labels" | 41526,162904 1 0 0 "CHK_ST\n/0/"
S 9 6 4096 ELLIPSE "States" | 41526,185122 6500 6500
L 8 9 0 TEXT "State Labels" | 41526,185122 1 0 0 "START_PRBY\n/1/"
G 1 0 0 TEXT 0,0,0 0 0 0 255,255,255 0 3527 1480 0000 0 "Arial" 0 | 93869,253485 1 0 0 "Module: processRxByte"
F 6 0 671089152 185 0 "" 0 RECT 0,0,0 0 0 1 255,255,255 0 | 14988,3000 199488,197598
L 7 6 0 TEXT "Labels" | 57079,194838 1 0 0 "prRxByte"
A 278 257 4 TEXT "Actions" | 130366,127109 1 0 0 "RxDataOutWEn <= 1'b0;\nRXByteStMachCurrState <= `IDLE_BYTE_ST;"
L 279 280 0 TEXT "State Labels" | 49504,129936 1 0 0 "FIN\n/10/"
S 280 41 69632 ELLIPSE "States" | 49504,129936 6500 6500
W 281 41 0 40 280 BEZIER "Transitions" | 71655,187272 66885,174036 56388,149316 51618,136080
A 282 280 4 TEXT "Actions" | 68321,131530 1 0 0 "CRC5En <= 1'b0;\nRxDataOutWEn <= 1'b0;"
W 284 41 0 280 37 BEZIER "Transitions" | 54276,125525 62504,119205 74052,104895 82280,98575
W 285 50 0 286 291 BEZIER "Transitions" | 59473,89872 67701,83552 79249,69242 87477,62922
S 286 50 73728 ELLIPSE "States" | 54701,94283 6500 6500
A 287 286 4 TEXT "Actions" | 73518,95877 1 0 0 "CRC16En <= 1'b0;\nRxDataOutWEn <= 1'b0;"
L 303 304 0 TEXT "Labels" | 84462,230495 1 0 0 "RxByteIn[7:0]"
I 302 0 2 Builtin OutPort | 76139,237545 "" ""
L 301 302 0 TEXT "Labels" | 82139,237545 1 0 0 "RxDataOutWEn"
I 300 0 130 Builtin OutPort | 76848,242565 "" ""
L 299 300 0 TEXT "Labels" | 82848,242565 1 0 0 "RxCtrlOut[7:0]"
I 298 0 130 Builtin OutPort | 76848,247579 "" ""
L 297 298 0 TEXT "Labels" | 82848,247579 1 0 0 "RxDataOut[7:0]"
A 296 0 1 TEXT "Actions" | 13933,252227 1 0 0 "always @\n(next_CRCError or next_bitStuffError or\n next_RxOverflow or next_NAKRxed or \n next_stallRxed or next_ACKRxed or \n next_dataSequence)\nbegin	\n  RxStatus <= \n  {1'b0, next_dataSequence, \n  next_ACKRxed, \n  next_stallRxed, next_NAKRxed, \n  next_RxOverflow, \n  next_bitStuffError, next_CRCError };\nend"
L 25 24 0 TEXT "State Labels" | 115892,81996 1 0 0 "HSHAKE"
S 24 6 8196 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 115892,81996 6500 6500
I 21 17 0 Builtin Exit | 89220,92674
I 20 17 0 Builtin Entry | 45216,248076
L 19 18 0 TEXT "State Labels" | 109233,155402 1 0 0 "FIRST_BYTE"
S 18 17 49156 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 109233,155402 6500 6500
H 17 16 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
S 16 6 12292 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 115714,110762 6500 6500
W 288 50 0 293 286 BEZIER "Transitions" | 76852,151619 72082,138383 61585,113663 56815,100427
L 289 286 0 TEXT "State Labels" | 54701,94283 1 0 0 "FIN\n/11/"
I 291 50 0 Builtin Exit | 90483,62922
I 292 50 0 Builtin Entry | 33692,252435
S 293 50 77824 ELLIPSE "States" | 79792,157415 6500 6500
L 294 293 0 TEXT "State Labels" | 79792,157415 1 0 0 "CHK_STRM\n/12/"
A 295 293 4 TEXT "Actions" | 114075,218259 1 0 0 "RXDataByteCnt <= RXDataByteCnt + 1'b1;\ncase (RxCtrl)\n  `DATA_STOP:\n  begin\n    if (CRC16Result != 16'hb001)\n      CRCError <= 1'b1;\n    RxDataOut <= RxStatus;\n    RxCtrlOut <= `RX_PACKET_STOP;\n    RXByteStMachCurrState <= `IDLE_BYTE_ST;\n  end\n  `DATA_BIT_STUFF_ERROR:\n  begin\n    bitStuffError <= 1'b1;\n    RxDataOut <= RxStatus;\n    RxCtrlOut <= `RX_PACKET_STOP;\n    RXByteStMachCurrState <= `IDLE_BYTE_ST;\n  end\n  `DATA_STREAM:\n  begin\n    RxDataOut <= RxByte;\n    RxCtrlOut <= `RX_PACKET_STREAM;\n    CRCData <= RxByte;\n    CRC16En <= 1'b1;\n  end\n  default:\n  begin\n    RXByteStMachCurrState <= `IDLE_BYTE_ST;\n  end\nendcase\nRxDataOutWEn <= 1'b1;"
L 319 320 0 TEXT "Labels" | 130127,218643 1 0 0 "CRC16En"
I 318 0 2 Builtin OutPort | 123866,228310 "" ""
L 317 318 0 TEXT "Labels" | 129866,228310 1 0 0 "CRC5_8Bit"
I 316 0 2 Builtin OutPort | 123509,232929 "" ""
L 315 316 0 TEXT "Labels" | 129509,232929 1 0 0 "CRC5En"
I 314 0 130 Builtin InPort | 125655,237903 "" ""
L 313 314 0 TEXT "Labels" | 131655,237903 1 0 0 "CRC5Result[4:0]"
I 312 0 130 Builtin OutPort | 123156,242520 "" ""
L 311 312 0 TEXT "Labels" | 129156,242520 1 0 0 "CRCData[7:0]"
I 310 0 2 Builtin OutPort | 123515,247488 "" ""
L 309 310 0 TEXT "Labels" | 129515,247488 1 0 0 "rstCRC"
I 308 0 2 Builtin InPort | 78462,219728 "" ""
L 307 308 0 TEXT "Labels" | 85176,219728 1 0 0 "processRxDataInWEn"
I 306 0 130 Builtin InPort | 78465,225472 "" ""
L 305 306 0 TEXT "Labels" | 84465,225472 1 0 0 "RxCtrlIn[7:0]"
I 304 0 130 Builtin InPort | 78462,230495 "" ""
L 43 42 0 TEXT "State Labels" | 118750,24108 1 0 0 "DATA"
S 42 6 16388 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 118750,24108 6500 6500
S 40 41 65536 ELLIPSE "States" | 74595,193068 6500 6500
L 39 40 0 TEXT "State Labels" | 74595,193068 1 0 0 "CHK_STRM\n/9/"
I 38 41 0 Builtin Entry | 30541,258592
I 37 41 0 Builtin Exit | 85286,98575
W 36 41 0 38 371 BEZIER "Transitions" | 34549,258592 38576,254357 47806,246433 31745,235718
L 34 33 0 TEXT "State Labels" | 117500,51980 1 0 0 "TOKEN"
S 33 6 20484 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 117500,51980 6500 6500
H 41 33 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
H 32 24 0 RECT 0,0,0 0 0 1 255,255,255 0 | 17144,15700 201644,263700
L 335 336 0 TEXT "Labels" | 175074,230643 1 0 0 "ACKRxed"
I 334 0 2 Builtin Signal | 172074,234927 "" ""
L 333 334 0 TEXT "Labels" | 175074,234927 1 0 0 "stallRxed"
I 332 0 2 Builtin Signal | 171717,239568 "" ""
L 331 332 0 TEXT "Labels" | 174717,239568 1 0 0 "NAKRxed"
I 330 0 2 Builtin Signal | 172074,243852 "" ""
L 329 330 0 TEXT "Labels" | 175074,243852 1 0 0 "RxTimeOut"