processrxbyte.v

对usb设备控制的ip核进行了重新设计并进一步优化

      begin
        NextState_prRxByte <= `CHK_PID_FIRST_BYTE_PROC;
        next_CRCError <= 1'b0;
        next_bitStuffError <= 1'b0;
        next_RxOverflow <= 1'b0;
        next_NAKRxed <= 1'b0;
        next_stallRxed <= 1'b0;
        next_ACKRxed <= 1'b0;
        next_dataSequence <= 1'b0;
        next_RxTimeOut <= 1'b0;
        next_RXDataByteCnt <= 10'h000;
        next_RxDataOut <= RxByte;
        next_RxCtrlOut <= `RX_PACKET_START;
        next_RxDataOutWEn <= 1'b1;
        next_rstCRC <= 1'b1;
      end
    `CHK_PID_FIRST_BYTE_PROC:
    begin
      next_rstCRC <= 1'b0;
      next_RxDataOutWEn <= 1'b0;
      case (RxByte[1:0] )
          `SPECIAL:                              //Special PID.
          next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
          `TOKEN:                                //Token PID
          begin
          next_RXByteStMachCurrState <= `TOKEN_BYTE_ST;
          next_RXDataByteCnt <= 0;
          end
          `HANDSHAKE:                            //Handshake PID
          begin
              case (RxByte[3:2] )
                  2'b00:
              next_ACKRxed <= 1'b1;
                  2'b10:
              next_NAKRxed <= 1'b1;
                  2'b11:
              next_stallRxed <= 1'b1;
                  default:
                  begin
                      $display ("Invalid Handshake PID detected in ProcessRXByte\n");
                  end
              endcase
          next_RXByteStMachCurrState <= `HS_BYTE_ST;
          end
          `DATA:                                  //Data PID
          begin
              case (RxByte[3:2] )
                  2'b00:
              next_dataSequence <= 1'b0;
                  2'b10:
              next_dataSequence <= 1'b1;
                  default:
                      $display ("Invalid DATA PID detected in ProcessRXByte\n");
              endcase
          next_RXByteStMachCurrState <= `DATA_BYTE_ST;
          next_RXDataByteCnt <= 0;
          end
      endcase
      NextState_prRxByte <= `WAIT_BYTE;
      next_processRxByteRdy <= 1'b1;
    end
    `DATA_FIN:
    begin
      next_CRC16En <= 1'b0;
      next_RxDataOutWEn <= 1'b0;
      NextState_prRxByte <= `WAIT_BYTE;
      next_processRxByteRdy <= 1'b1;
    end
    `DATA_CHK_STRM:
    begin
      next_RXDataByteCnt <= RXDataByteCnt + 1'b1;
      case (RxCtrl)
          `DATA_STOP:
          begin
              if (CRC16Result != 16'hb001)
            next_CRCError <= 1'b1;
          next_RxDataOut <= RxStatus;
          next_RxCtrlOut <= `RX_PACKET_STOP;
          next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
          end
          `DATA_BIT_STUFF_ERROR:
          begin
          next_bitStuffError <= 1'b1;
          next_RxDataOut <= RxStatus;
          next_RxCtrlOut <= `RX_PACKET_STOP;
          next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
          end
          `DATA_STREAM:
          begin
          next_RxDataOut <= RxByte;
          next_RxCtrlOut <= `RX_PACKET_STREAM;
          next_CRCData <= RxByte;
          next_CRC16En <= 1'b1;
          end
          default:
          begin
          next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
          end
      endcase
      next_RxDataOutWEn <= 1'b1;
      NextState_prRxByte <= `DATA_FIN;
    end
    `DATA_WAIT_CRC:
      if (CRC16UpdateRdy == 1'b1)	
        NextState_prRxByte <= `DATA_CHK_STRM;
    `TOKEN_CHK_STRM:
    begin
      next_RXDataByteCnt <= RXDataByteCnt + 1'b1;
      case (RxCtrl)
          `DATA_STOP:
          begin
              if (CRC5Result != 5'h6)
            next_CRCError <= 1'b1;
          next_RxDataOut <= RxStatus;
          next_RxCtrlOut <= `RX_PACKET_STOP;
          next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
          end
          `DATA_BIT_STUFF_ERROR:
          begin
          next_bitStuffError <= 1'b1;
          next_RxDataOut <= RxStatus;
          next_RxCtrlOut <= `RX_PACKET_STOP;
          next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
          end
          `DATA_STREAM:
          begin
              if (RXDataByteCnt > 10'h2)
              begin
            next_RxOverflow <= 1'b1;
            next_RxDataOut <= RxStatus;
            next_RxCtrlOut <= `RX_PACKET_STOP;
            next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
              end
              else
              begin
            next_RxDataOut <= RxByte;
            next_RxCtrlOut <= `RX_PACKET_STREAM;
            next_CRCData <= RxByte;
            next_CRC5_8Bit <= 1'b1;
            next_CRC5En <= 1'b1;
              end
          end
          default:
          begin
          next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
          end
      endcase
      next_RxDataOutWEn <= 1'b1;
      NextState_prRxByte <= `TOKEN_FIN;
    end
    `TOKEN_FIN:
    begin
      next_CRC5En <= 1'b0;
      next_RxDataOutWEn <= 1'b0;
      NextState_prRxByte <= `WAIT_BYTE;
      next_processRxByteRdy <= 1'b1;
    end
    `TOKEN_WAIT_CRC:
      if (CRC5UpdateRdy == 1'b1)	
        NextState_prRxByte <= `TOKEN_CHK_STRM;
    `CHK_SYNC_DO:
    begin
      if (RxByte == `SYNC_BYTE)
        next_RXByteStMachCurrState <= `CHECK_PID_ST;
      else
        next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
      NextState_prRxByte <= `WAIT_BYTE;
      next_processRxByteRdy <= 1'b1;
    end
    `IDLE_CHK_START:
    begin
      if (RxCtrl == `DATA_START)
        next_RXByteStMachCurrState <= `CHECK_SYNC_ST;
      NextState_prRxByte <= `WAIT_BYTE;
      next_processRxByteRdy <= 1'b1;
    end
  endcase
end

//----------------------------------
// Current State Logic (sequential)
//----------------------------------
always @ (posedge clk)
begin : prRxByte_CurrentState
  if (rst)	
    CurrState_prRxByte <= `START_PRBY;
  else
    CurrState_prRxByte <= NextState_prRxByte;
end

//----------------------------------
// Registered outputs logic
//----------------------------------
always @ (posedge clk)
begin : prRxByte_RegOutput
  if (rst)	
  begin
    RxByte <= 8'h00;
    RxCtrl <= 8'h00;
    RXByteStMachCurrState <= `IDLE_BYTE_ST;
    CRCError <= 1'b0;
    bitStuffError <= 1'b0;
    RxOverflow <= 1'b0;
    RxTimeOut <= 1'b0;
    NAKRxed <= 1'b0;
    stallRxed <= 1'b0;
    ACKRxed <= 1'b0;
    dataSequence <= 1'b0;
    RXDataByteCnt <= 10'h00;
    RxDataOut <= 8'h00;
    RxCtrlOut <= 8'h00;
    RxDataOutWEn <= 1'b0;
    rstCRC <= 1'b0;
    CRCData <= 8'h00;
    CRC5En <= 1'b0;
    CRC5_8Bit <= 1'b0;
    CRC16En <= 1'b0;
    processRxByteRdy <= 1'b1;
  end
  else 
  begin
    RxByte <= next_RxByte;
    RxCtrl <= next_RxCtrl;
    RXByteStMachCurrState <= next_RXByteStMachCurrState;
    CRCError <= next_CRCError;
    bitStuffError <= next_bitStuffError;
    RxOverflow <= next_RxOverflow;
    RxTimeOut <= next_RxTimeOut;
    NAKRxed <= next_NAKRxed;
    stallRxed <= next_stallRxed;
    ACKRxed <= next_ACKRxed;
    dataSequence <= next_dataSequence;
    RXDataByteCnt <= next_RXDataByteCnt;
    RxDataOut <= next_RxDataOut;
    RxCtrlOut <= next_RxCtrlOut;
    RxDataOutWEn <= next_RxDataOutWEn;
    rstCRC <= next_rstCRC;
    CRCData <= next_CRCData;
    CRC5En <= next_CRC5En;
    CRC5_8Bit <= next_CRC5_8Bit;
    CRC16En <= next_CRC16En;
    processRxByteRdy <= next_processRxByteRdy;
  end
end

endmodule