__projnav.log

微波爐．．．．．．．．．．．．．．．．．．．．．．．．．．

=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "D:/KSC/lab2/PICunit.vhd" in Library work.
Entity <picunit> compiled.
ERROR:HDLParsers:164 - "D:/KSC/lab2/PICunit.vhd" Line 73. parse error, unexpected PIPE, expecting THEN
ERROR:HDLParsers:164 - "D:/KSC/lab2/PICunit.vhd" Line 79. parse error, unexpected IF, expecting PROCESS
--> 

Total memory usage is 75976 kilobytes

Number of errors   :    2 (   0 filtered)
Number of warnings :    0 (   0 filtered)
Number of infos    :    0 (   0 filtered)

ERROR: XST failed
Process "Synthesize" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------










Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "D:/KSC/lab2/PICunit.vhd" in Library work.
Entity <picunit> compiled.
Entity <picunit> (Architecture <behavioral>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <picunit> (Architecture <behavioral>).
Entity <picunit> analyzed. Unit <picunit> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <picunit>.
    Related source file is "D:/KSC/lab2/PICunit.vhd".
    Found 1-bit register for signal <Key_EN>.
    Found 1-bit register for signal <Counter_Reset>.
    Found 1-bit register for signal <EN>.
    Found 3-bit register for signal <temp_LED>.
    Summary:
	inferred   6 D-type flip-flop(s).
Unit <picunit> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Registers                        : 4
 1-bit register                    : 3
 3-bit register                    : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <picunit> ...
Loading device for application Rf_Device from file '2s50e.nph' in environment c:/xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block picunit, actual ratio is 1.

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s50etq144-6 

 Number of Slices:                       7  out of    768     0%  
 Number of Slice Flip Flops:             6  out of   1536     0%  
 Number of 4 input LUTs:                 8  out of   1536     0%  
 Number of bonded IOBs:                 15  out of    102    14%  
 Number of GCLKs:                        1  out of      4    25%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
PIC_clk                            | BUFGP                  | 6     |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: 3.334ns (Maximum Frequency: 299.940MHz)
   Minimum input arrival time before clock: 4.682ns
   Maximum output required time after clock: 6.744ns
   Maximum combinational path delay: No path found

=========================================================================


Project Navigator Auto-Make Log File
-------------------------------------










Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "D:/KSC/lab2/PICunit.vhd" in Library work.
Architecture behavioral of Entity picunit is up to date.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <picunit> (Architecture <behavioral>).
Entity <picunit> analyzed. Unit <picunit> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <picunit>.
    Related source file is "D:/KSC/lab2/PICunit.vhd".
    Found 1-bit register for signal <Key_EN>.
    Found 1-bit register for signal <Counter_Reset>.
    Found 1-bit register for signal <EN>.
    Found 3-bit register for signal <temp_LED>.
    Summary:
	inferred   6 D-type flip-flop(s).
Unit <picunit> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Registers                        : 4
 1-bit register                    : 3
 3-bit register                    : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <picunit> ...
Loading device for application Rf_Device from file '2s50e.nph' in environment c:/xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block picunit, actual ratio is 1.

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s50etq144-6 

 Number of Slices:                       7  out of    768     0%  
 Number of Slice Flip Flops:             6  out of   1536     0%  
 Number of 4 input LUTs:                 8  out of   1536     0%  
 Number of bonded IOBs:                 15  out of    102    14%  
 Number of GCLKs:                        1  out of      4    25%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
PIC_clk                            | BUFGP                  | 6     |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: 3.334ns (Maximum Frequency: 299.940MHz)
   Minimum input arrival time before clock: 4.682ns
   Maximum output required time after clock: 6.744ns
   Maximum combinational path delay: No path found

=========================================================================




Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd d:\ksc\lab2/_ngo -nt timestamp -i -p
xc2s50e-tq144-6 picunit.ngc picunit.ngd 

Reading NGO file 'D:/KSC/lab2/picunit.ngc' ...

Checking timing specifications ...
Checking expanded design ...

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   0

Writing NGD file "picunit.ngd" ...

Writing NGDBUILD log file "picunit.bld"...

NGDBUILD done.




Started process "Map".

Using target part "2s50etq144-6".
Mapping design into LUTs...
Running directed packing...
Running delay-based LUT packing...
Running related packing...

Design Summary:
Number of errors:      0
Number of warnings:    0
Logic Utilization:
  Number of Slice Flip Flops:         4 out of  1,536    1%
  Number of 4 input LUTs:             8 out of  1,536    1%
Logic Distribution:
    Number of occupied Slices:                           5 out of    768    1%
    Number of Slices containing only related logic:      5 out of      5  100%
    Number of Slices containing unrelated logic:         0 out of      5    0%
        *See NOTES below for an explanation of the effects of unrelated logic
Total Number of 4 input LUTs:         8 out of  1,536    1%
   Number of bonded IOBs:            14 out of     98   14%
      IOB Flip Flops:                               2
   Number of GCLKs:                   1 out of      4   25%
   Number of GCLKIOBs:                1 out of      4   25%

Total equivalent gate count for design:  96
Additional JTAG gate count for IOBs:  720
Peak Memory Usage:  95 MB

NOTES:

   Related logic is defined as being logic that shares connectivity - e.g. two
   LUTs are "related" if they share common inputs.  When assembling slices,
   Map gives priority to combine logic that is related.  Doing so results in
   the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin packing
   unrelated logic into a slice once 99% of the slices are occupied through
   related logic packing.

   Note that once logic distribution reaches the 99% level through related
   logic packing, this does not mean the device is completely utilized.
   Unrelated logic packing will then begin, continuing until all usable LUTs
   and FFs are occupied.  Depending on your timing budget, increased levels of
   unrelated logic packing may adversely affect the overall timing performance
   of your design.

Mapping completed.
See MAP report file "picunit_map.mrp" for details.




Started process "Place & Route".




Constraints file: picunit.pcf.
Loading device for application Rf_Device from file '2s50e.nph' in environment
c:/xilinx.
   "picunit" is an NCD, version 3.1, device xc2s50e, package tq144, speed -6

Initializing temperature to 85.000 Celsius. (default - Range: -40.000 to 85.000
Celsius)
Initializing voltage to 1.700 Volts. (default - Range: 1.700 to 1.900 Volts)


Device speed data version:  "PRODUCTION 1.18 2005-01-22".


Device Utilization Summary:

   Number of GCLKs                     1 out of 4      25%
   Number of External GCLKIOBs         1 out of 4      25%
      Number of LOCed GCLKIOBs         0 out of 1       0%

   Number of External IOBs            14 out of 98     14%
      Number of LOCed IOBs             0 out of 14      0%

   Number of SLICEs                    5 out of 768     1%


Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)


Starting Placer

Phase 1.1
Phase 1.1 (Checksum:9896d3) REAL time: 0 secs 

Phase 2.31
Phase 2.31 (Checksum:1312cfe) REAL time: 0 secs 

Phase 3.23
Phase 3.23 (Checksum:1c9c37d) REAL time: 0 secs 

Phase 4.3
Phase 4.3 (Checksum:26259fc) REAL time: 0 secs 

Phase 5.5
Phase 5.5 (Checksum:2faf07b) REAL time: 0 secs 

Phase 6.8
.
Phase 6.8 (Checksum:98afcf) REAL time: 0 secs 

Phase 7.5
Phase 7.5 (Checksum:42c1d79) REAL time: 0 secs 

Phase 8.18
Phase 8.18 (Checksum:4c4b3f8) REAL time: 0 secs 

Phase 9.5
Phase 9.5 (Checksum:55d4a77) REAL time: 0 secs 

Writing design to file picunit.ncd


Total REAL time to Placer completion: 0 secs 
Total CPU time to Placer completion: 0 secs 

Starting Router

Phase 1: 42 unrout