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微波爐．．．．．．．．．．．．．．．．．．．．．．．．．．

Analyzing Entity <clkdiv2> (Architecture <behavioral>).
Entity <clkdiv2> analyzed. Unit <clkdiv2> generated.

Analyzing Entity <seven_segnment> (Architecture <behavioral>).
INFO:Xst:1561 - "D:/KSC/lab2/seven_segnment.vhd" line 69: Mux is complete : default of case is discarded
Entity <seven_segnment> analyzed. Unit <seven_segnment> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <seven_segnment>.
    Related source file is "D:/KSC/lab2/seven_segnment.vhd".
    Found 16x7-bit ROM for signal <output>.
    Summary:
	inferred   1 ROM(s).
Unit <seven_segnment> synthesized.


Synthesizing Unit <clkdiv2>.
    Related source file is "D:/KSC/lab2/clkdiv2.vhd".
    Found 6-bit adder for signal <$n0011> created at line 55.
    Found 6-bit adder for signal <$n0012> created at line 59.
    Found 1-bit register for signal <A>.
    Found 1-bit register for signal <B>.
    Found 6-bit up counter for signal <counta>.
    Found 6-bit up counter for signal <countb>.
    Found 6-bit register for signal <countc>.
    Found 6-bit register for signal <countd>.
    Summary:
	inferred   2 Counter(s).
	inferred  14 D-type flip-flop(s).
	inferred   2 Adder/Subtractor(s).
Unit <clkdiv2> synthesized.


Synthesizing Unit <counter>.
    Related source file is "D:/KSC/lab2/counter.vhd".
    Found 1-bit register for signal <TC>.
    Found 4-bit down counter for signal <COUNT>.
    Summary:
	inferred   1 Counter(s).
	inferred   1 D-type flip-flop(s).
Unit <counter> synthesized.


Synthesizing Unit <key_number_encoder>.
    Related source file is "D:/KSC/lab2/key_number_encoder.vhd".
    Found 1-bit register for signal <kload>.
    Found 4-bit register for signal <Qn>.
    Summary:
	inferred   5 D-type flip-flop(s).
Unit <key_number_encoder> synthesized.


Synthesizing Unit <PICunit>.
    Related source file is "D:/KSC/lab2/PICunit.vhd".
    Found 1-bit register for signal <Counter_Reset>.
    Found 1-bit register for signal <Key_EN>.
    Found 1-bit register for signal <EN>.
    Found 3-bit register for signal <temp_LED>.
    Summary:
	inferred   6 D-type flip-flop(s).
Unit <PICunit> synthesized.


Synthesizing Unit <microoven>.
    Related source file is "D:/KSC/lab2/microoven.vhd".
Unit <microoven> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# ROMs                             : 1
 16x7-bit ROM                      : 1
# Adders/Subtractors               : 2
 6-bit adder                       : 2
# Counters                         : 3
 4-bit down counter                : 1
 6-bit up counter                  : 2
# Registers                        : 11
 1-bit register                    : 7
 3-bit register                    : 1
 4-bit register                    : 1
 6-bit register                    : 2

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <microoven> ...

Optimizing unit <counter> ...

Optimizing unit <clkdiv2> ...

Optimizing unit <key_number_encoder> ...

Optimizing unit <PICunit> ...
Loading device for application Rf_Device from file '2s50e.nph' in environment c:/xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block microoven, actual ratio is 8.

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s50etq144-6 

 Number of Slices:                      60  out of    768     7%  
 Number of Slice Flip Flops:            42  out of   1536     2%  
 Number of 4 input LUTs:                94  out of   1536     6%  
 Number of bonded IOBs:                 25  out of    102    24%  
 Number of GCLKs:                        1  out of      4    25%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
u4/B:Q                             | NONE                   | 10    |
Clk                                | BUFGP                  | 26    |
u4/A:Q                             | NONE                   | 6     |
-----------------------------------+------------------------+-------+
INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: 9.033ns (Maximum Frequency: 110.705MHz)
   Minimum input arrival time before clock: 8.203ns
   Maximum output required time after clock: 9.432ns
   Maximum combinational path delay: No path found

=========================================================================




Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd d:\ksc\lab2/_ngo -nt timestamp -uc
micooven.ucf -p xc2s50e-tq144-6 microoven.ngc microoven.ngd 

Reading NGO file 'D:/KSC/lab2/microoven.ngc' ...

Applying constraints in "micooven.ucf" to the design...

Checking timing specifications ...
Checking expanded design ...

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   0

Writing NGD file "microoven.ngd" ...

Writing NGDBUILD log file "microoven.bld"...

NGDBUILD done.




Started process "Map".

Using target part "2s50etq144-6".
Mapping design into LUTs...
Running directed packing...
Running delay-based LUT packing...
Running related packing...

Design Summary:
Number of errors:      0
Number of warnings:    0
Logic Utilization:
  Number of Slice Flip Flops:        42 out of  1,536    2%
  Number of 4 input LUTs:            78 out of  1,536    5%
Logic Distribution:
    Number of occupied Slices:                          57 out of    768    7%
    Number of Slices containing only related logic:     57 out of     57  100%
    Number of Slices containing unrelated logic:         0 out of     57    0%
        *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:           98 out of  1,536    6%
      Number used as logic:                        78
      Number used as a route-thru:                 20
   Number of bonded IOBs:            24 out of     98   24%
   Number of GCLKs:                   1 out of      4   25%
   Number of GCLKIOBs:                1 out of      4   25%

Total equivalent gate count for design:  927
Additional JTAG gate count for IOBs:  1,200
Peak Memory Usage:  96 MB

NOTES:

   Related logic is defined as being logic that shares connectivity - e.g. two
   LUTs are "related" if they share common inputs.  When assembling slices,
   Map gives priority to combine logic that is related.  Doing so results in
   the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin packing
   unrelated logic into a slice once 99% of the slices are occupied through
   related logic packing.

   Note that once logic distribution reaches the 99% level through related
   logic packing, this does not mean the device is completely utilized.
   Unrelated logic packing will then begin, continuing until all usable LUTs
   and FFs are occupied.  Depending on your timing budget, increased levels of
   unrelated logic packing may adversely affect the overall timing performance
   of your design.

Mapping completed.
See MAP report file "microoven_map.mrp" for details.




Started process "Place & Route".




Constraints file: microoven.pcf.
Loading device for application Rf_Device from file '2s50e.nph' in environment
c:/xilinx.
   "microoven" is an NCD, version 3.1, device xc2s50e, package tq144, speed -6

Initializing temperature to 85.000 Celsius. (default - Range: -40.000 to 85.000
Celsius)
Initializing voltage to 1.700 Volts. (default - Range: 1.700 to 1.900 Volts)


Device speed data version:  "PRODUCTION 1.18 2005-01-22".


Device Utilization Summary:

   Number of GCLKs                     1 out of 4      25%
   Number of External GCLKIOBs         1 out of 4      25%
      Number of LOCed GCLKIOBs         1 out of 1     100%

   Number of External IOBs            24 out of 98     24%
      Number of LOCed IOBs            24 out of 24    100%

   Number of SLICEs                   57 out of 768     7%


Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)


Starting Placer

Phase 1.1
Phase 1.1 (Checksum:9897f6) REAL time: 0 secs 

Phase 2.31
Phase 2.31 (Checksum:1312cfe) REAL time: 0 secs 

Phase 3.23
Phase 3.23 (Checksum:1c9c37d) REAL time: 0 secs 

Phase 4.3
Phase 4.3 (Checksum:26259fc) REAL time: 0 secs 

Phase 5.5
Phase 5.5 (Checksum:2faf07b) REAL time: 0 secs 

Phase 6.8
.....
Phase 6.8 (Checksum:99f2e5) REAL time: 0 secs 

Phase 7.5
Phase 7.5 (Checksum:42c1d79) REAL time: 0 secs 

Phase 8.18
Phase 8.18 (Checksum:4c4b3f8) REAL time: 0 secs 

Phase 9.5
Phase 9.5 (Checksum:55d4a77) REAL time: 0 secs 

Writing design to file microoven.ncd


Total REAL time to Placer completion: 0 secs 
Total CPU time to Placer completion: 0 secs 

Starting Router

Phase 1: 390 unrouted;       REAL time: 0 secs 

Phase 2: 366 unrouted;       REAL time: 0 secs 

Phase 3: 72 unrouted;       REAL time: 0 secs 

Phase 4: 0 unrouted;       REAL time: 0 secs 

Total REAL time to Router completion: 0 secs 
Total CPU time to Router completion: 0 secs 

Generating "PAR" statistics.

**************************
Generating Clock Report
**************************

+---------------------+--------------+------+------+------------+-------------+
|        Clock Net    |   Resource   |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
|           Clk_BUFGP |      GCLKBUF0| No   |   16 |  0.056     |  0.400      |
+---------------------+--------------+------+------+------------+-------------+
|                u4/B |      Low-Skew|      |   11 |  0.192     |  4.444      |
+---------------------+--------------+------+------+------------+-------------+
|                u4/A |         Local|      |    6 |  1.902     |  3.362      |
+---------------------+--------------+------+------+------------+-------------+

Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 1 secs 
Total CPU time to PAR completion: 1 secs 

Peak Memory Usage:  69 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Number of error messages: 0
Number of warning messages: 0
Number of info messages: 1

Writing design to file microoven.ncd



PAR done!

Started process "Generate Post-Place & Route Static Timing".

Loading device for application Rf_Device from file '2s50e.nph' in environment
c:/xilinx.
   "microoven" is an NCD, version 3.1, device xc2s50e, package tq144, speed -6

Analysis completed Mon Mar 09 12:15:00 2009
--------------------------------------------------------------------------------

Generating Report ...

Number of warnings: 0
Total time: 0 secs 







Started process "Generate Programming File".



Project Navigator Auto-Make Log File
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Started process "Synthesize".