__projnav.log

微波爐．．．．．．．．．．．．．．．．．．．．．．．．．．

Checksum:99f82b) REAL time: 0 secs 

Phase 7.5
Phase 7.5 (Checksum:42c1d79) REAL time: 0 secs 

Phase 8.18
Phase 8.18 (Checksum:4c4b3f8) REAL time: 0 secs 

Phase 9.5
Phase 9.5 (Checksum:55d4a77) REAL time: 0 secs 

Writing design to file microoven.ncd


Total REAL time to Placer completion: 0 secs 
Total CPU time to Placer completion: 0 secs 

Starting Router

Phase 1: 389 unrouted;       REAL time: 0 secs 

Phase 2: 366 unrouted;       REAL time: 0 secs 

Phase 3: 78 unrouted;       REAL time: 1 secs 

Phase 4: 0 unrouted;       REAL time: 1 secs 

Total REAL time to Router completion: 1 secs 
Total CPU time to Router completion: 1 secs 

Generating "PAR" statistics.

**************************
Generating Clock Report
**************************

+---------------------+--------------+------+------+------------+-------------+
|        Clock Net    |   Resource   |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
|           Clk_BUFGP |      GCLKBUF0| No   |   16 |  0.052     |  0.399      |
+---------------------+--------------+------+------+------------+-------------+
|                u4/B |         Local|      |   11 |  1.235     |  3.380      |
+---------------------+--------------+------+------+------------+-------------+
|                u4/A |         Local|      |    6 |  2.092     |  3.185      |
+---------------------+--------------+------+------+------------+-------------+

Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 1 secs 
Total CPU time to PAR completion: 1 secs 

Peak Memory Usage:  69 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Number of error messages: 0
Number of warning messages: 0
Number of info messages: 1

Writing design to file microoven.ncd



PAR done!

Started process "Generate Post-Place & Route Static Timing".

Loading device for application Rf_Device from file '2s50e.nph' in environment
c:/xilinx.
   "microoven" is an NCD, version 3.1, device xc2s50e, package tq144, speed -6

Analysis completed Mon Mar 09 12:10:50 2009
--------------------------------------------------------------------------------

Generating Report ...

Number of warnings: 0
Total time: 0 secs 







Started process "Generate Programming File".



Project Navigator Auto-Make Log File
-------------------------------------










Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "D:/KSC/lab2/PICunit.vhd" in Library work.
Entity <picunit> compiled.
Entity <picunit> (Architecture <behavioral>) compiled.
Compiling vhdl file "D:/KSC/lab2/key_number_encoder.vhd" in Library work.
Architecture behavioral of Entity key_number_encoder is up to date.
Compiling vhdl file "D:/KSC/lab2/counter.vhd" in Library work.
Architecture behavioral of Entity counter is up to date.
Compiling vhdl file "D:/KSC/lab2/clkdiv2.vhd" in Library work.
Architecture behavioral of Entity clkdiv2 is up to date.
Compiling vhdl file "D:/KSC/lab2/seven_segnment.vhd" in Library work.
Architecture behavioral of Entity seven_segnment is up to date.
Compiling vhdl file "D:/KSC/lab2/microoven.vhd" in Library work.
Architecture behavioral of Entity microoven is up to date.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <microoven> (Architecture <behavioral>).
Entity <microoven> analyzed. Unit <microoven> generated.

Analyzing Entity <PICunit> (Architecture <behavioral>).
Entity <PICunit> analyzed. Unit <PICunit> generated.

Analyzing Entity <key_number_encoder> (Architecture <behavioral>).
Entity <key_number_encoder> analyzed. Unit <key_number_encoder> generated.

Analyzing Entity <counter> (Architecture <behavioral>).
Entity <counter> analyzed. Unit <counter> generated.

Analyzing Entity <clkdiv2> (Architecture <behavioral>).
Entity <clkdiv2> analyzed. Unit <clkdiv2> generated.

Analyzing Entity <seven_segnment> (Architecture <behavioral>).
INFO:Xst:1561 - "D:/KSC/lab2/seven_segnment.vhd" line 69: Mux is complete : default of case is discarded
Entity <seven_segnment> analyzed. Unit <seven_segnment> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <seven_segnment>.
    Related source file is "D:/KSC/lab2/seven_segnment.vhd".
    Found 16x7-bit ROM for signal <output>.
    Summary:
	inferred   1 ROM(s).
Unit <seven_segnment> synthesized.


Synthesizing Unit <clkdiv2>.
    Related source file is "D:/KSC/lab2/clkdiv2.vhd".
    Found 6-bit adder for signal <$n0011> created at line 55.
    Found 6-bit adder for signal <$n0012> created at line 59.
    Found 1-bit register for signal <A>.
    Found 1-bit register for signal <B>.
    Found 6-bit up counter for signal <counta>.
    Found 6-bit up counter for signal <countb>.
    Found 6-bit register for signal <countc>.
    Found 6-bit register for signal <countd>.
    Summary:
	inferred   2 Counter(s).
	inferred  14 D-type flip-flop(s).
	inferred   2 Adder/Subtractor(s).
Unit <clkdiv2> synthesized.


Synthesizing Unit <counter>.
    Related source file is "D:/KSC/lab2/counter.vhd".
    Found 1-bit register for signal <TC>.
    Found 4-bit down counter for signal <COUNT>.
    Summary:
	inferred   1 Counter(s).
	inferred   1 D-type flip-flop(s).
Unit <counter> synthesized.


Synthesizing Unit <key_number_encoder>.
    Related source file is "D:/KSC/lab2/key_number_encoder.vhd".
    Found 1-bit register for signal <kload>.
    Found 4-bit register for signal <Qn>.
    Summary:
	inferred   5 D-type flip-flop(s).
Unit <key_number_encoder> synthesized.


Synthesizing Unit <PICunit>.
    Related source file is "D:/KSC/lab2/PICunit.vhd".
    Found 1-bit register for signal <Counter_Reset>.
    Found 1-bit register for signal <Key_EN>.
    Found 1-bit register for signal <EN>.
    Found 3-bit register for signal <temp_LED>.
    Summary:
	inferred   6 D-type flip-flop(s).
Unit <PICunit> synthesized.


Synthesizing Unit <microoven>.
    Related source file is "D:/KSC/lab2/microoven.vhd".
Unit <microoven> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# ROMs                             : 1
 16x7-bit ROM                      : 1
# Adders/Subtractors               : 2
 6-bit adder                       : 2
# Counters                         : 3
 4-bit down counter                : 1
 6-bit up counter                  : 2
# Registers                        : 11
 1-bit register                    : 7
 3-bit register                    : 1
 4-bit register                    : 1
 6-bit register                    : 2

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <microoven> ...

Optimizing unit <counter> ...

Optimizing unit <clkdiv2> ...

Optimizing unit <key_number_encoder> ...

Optimizing unit <PICunit> ...
Loading device for application Rf_Device from file '2s50e.nph' in environment c:/xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block microoven, actual ratio is 8.

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s50etq144-6 

 Number of Slices:                      60  out of    768     7%  
 Number of Slice Flip Flops:            42  out of   1536     2%  
 Number of 4 input LUTs:                94  out of   1536     6%  
 Number of bonded IOBs:                 25  out of    102    24%  
 Number of GCLKs:                        1  out of      4    25%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
u4/B:Q                             | NONE                   | 10    |
Clk                                | BUFGP                  | 26    |
u4/A:Q                             | NONE                   | 6     |
-----------------------------------+------------------------+-------+
INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: 9.033ns (Maximum Frequency: 110.705MHz)
   Minimum input arrival time before clock: 8.203ns
   Maximum output required time after clock: 9.432ns
   Maximum combinational path delay: No path found

=========================================================================


Project Navigator Auto-Make Log File
-------------------------------------










Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "D:/KSC/lab2/PICunit.vhd" in Library work.
Architecture behavioral of Entity picunit is up to date.
Compiling vhdl file "D:/KSC/lab2/key_number_encoder.vhd" in Library work.
Architecture behavioral of Entity key_number_encoder is up to date.
Compiling vhdl file "D:/KSC/lab2/counter.vhd" in Library work.
Architecture behavioral of Entity counter is up to date.
Compiling vhdl file "D:/KSC/lab2/clkdiv2.vhd" in Library work.
Architecture behavioral of Entity clkdiv2 is up to date.
Compiling vhdl file "D:/KSC/lab2/seven_segnment.vhd" in Library work.
Architecture behavioral of Entity seven_segnment is up to date.
Compiling vhdl file "D:/KSC/lab2/microoven.vhd" in Library work.
Architecture behavioral of Entity microoven is up to date.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <microoven> (Architecture <behavioral>).
Entity <microoven> analyzed. Unit <microoven> generated.

Analyzing Entity <PICunit> (Architecture <behavioral>).
Entity <PICunit> analyzed. Unit <PICunit> generated.

Analyzing Entity <key_number_encoder> (Architecture <behavioral>).
Entity <key_number_encoder> analyzed. Unit <key_number_encoder> generated.

Analyzing Entity <counter> (Architecture <behavioral>).
Entity <counter> analyzed. Unit <counter> generated.

Analyzing Entity <clkdiv2> (Architecture <behavioral>).
Entity <clkdiv2> analyzed. Unit <clkdiv2> generated.

Analyzing Entity <seven_segnment> (Architecture <behavioral>).
INFO:Xst:1561 - "D:/KSC/lab2/seven_segnment.vhd" line 69: Mux is complete : default of case is discarded
Entity <seven_segnment> analyzed. Unit <seven_segnment> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <seven_segnment>.
    Related source file is "D:/KSC/lab2/seven_segnment.vhd".
    Found 16x7-bit ROM for signal <output>.
    Summary:
	inferred   1 ROM(s).
Unit <seven_segnment> synthesized.


Synthesizing Unit <clkdiv2>.
    Related source file is "D:/KSC/lab2/clkdiv2.vhd".
    Found 6-bit adder for signal <$n0011> created at line 55.
    Found 6-bit adder for signal <$n0012> created at line 59.
    Found 1-bit register for signal <A>.
    Found 1-bit register for signal <B>.
    Found 6-bit up counter for signal <counta>.
    Found 6-bit up counter for signal <countb>.
    Found 6-bit register for signal <countc>.
    Found 6-bit register for signal <countd>.
    Summary:
	inferred   2 Counter(s).
	inferred  14 D-type flip-flop(s).
	inferred   2 Adder/Subtractor(s).
Unit <clkdiv2> synthesized.


Synthesizing Unit <counter>.
    Related source file is "D:/KSC/lab2/counter.vhd".
    Found 1-bit register for signal <TC>.
    Found 4-bit down counter for signal <COUNT>.
    Summary:
	inferred   1 Counter(s).
	inferred   1 D-type flip-flop(s).
Unit <counter> synthesized.


Synthesizing Unit <key_number_encoder>.
    Related source file is "D:/KSC/lab2/key_number_encoder.vhd".
    Found 1-bit register for signal <kload>.
    Found 4-bit register for signal <Qn>.
    Summary:
	inferred   5 D-type flip-flop(s).
Unit <key_number_encoder> synthesized.


Synthesizing Unit <PICunit>.