microoven_timesim.vhd

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      I => u4_counta_n0000_2_Q,
      CE => VCC,
      CLK => Clk_BUFGP,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => u4_n0005_0,
      O => u4_counta_2_Q
    );
  u4_counta_2_LOGIC_ZERO_25 : X_ZERO
    port map (
      O => u4_counta_2_LOGIC_ZERO
    );
  u4_clkdiv2_counta_n0000_2_cy : X_MUX2
    port map (
      IA => u4_counta_2_LOGIC_ZERO,
      IB => u4_counta_2_CYINIT,
      SEL => u4_counta_2_FROM,
      O => u4_clkdiv2_counta_n0000_2_cyo
    );
  u4_clkdiv2_counta_n0000_2_xor : X_XOR2
    port map (
      I0 => u4_counta_2_CYINIT,
      I1 => u4_counta_2_FROM,
      O => u4_counta_n0000_2_Q
    );
  u4_counta_2_F : X_LUT4
    generic map(
      INIT => X"FF00"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => u4_counta_2_Q,
      O => u4_counta_2_FROM
    );
  u4_counta_2_G : X_LUT4
    generic map(
      INIT => X"CCCC"
    )
    port map (
      ADR0 => VCC,
      ADR1 => u4_counta_3_Q,
      ADR2 => VCC,
      ADR3 => VCC,
      O => u4_counta_2_GROM
    );
  u4_clkdiv2_counta_n0000_3_cy : X_MUX2
    port map (
      IA => u4_counta_2_LOGIC_ZERO,
      IB => u4_clkdiv2_counta_n0000_2_cyo,
      SEL => u4_counta_2_GROM,
      O => u4_counta_2_CYMUXG
    );
  u4_clkdiv2_counta_n0000_3_xor : X_XOR2
    port map (
      I0 => u4_clkdiv2_counta_n0000_2_cyo,
      I1 => u4_counta_2_GROM,
      O => u4_counta_n0000_3_Q
    );
  u4_counta_2_CYINIT_26 : X_BUF
    port map (
      I => u4_counta_0_CYMUXG,
      O => u4_counta_2_CYINIT
    );
  u4_n0010_4_LOGIC_ZERO_27 : X_ZERO
    port map (
      O => u4_n0010_4_LOGIC_ZERO
    );
  u4_clkdiv2_n0010_4_cy : X_MUX2
    port map (
      IA => u4_n0010_4_LOGIC_ZERO,
      IB => u4_n0010_4_CYINIT,
      SEL => u4_n0010_4_FROM,
      O => u4_clkdiv2_n0010_4_cyo
    );
  u4_clkdiv2_n0010_4_xor : X_XOR2
    port map (
      I0 => u4_n0010_4_CYINIT,
      I1 => u4_n0010_4_FROM,
      O => u4_n0010_4_Q
    );
  u4_n0010_4_F : X_LUT4
    generic map(
      INIT => X"F0F0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => u4_countd_4_Q,
      ADR3 => VCC,
      O => u4_n0010_4_FROM
    );
  u4_countd_5_rt_28 : X_LUT4
    generic map(
      INIT => X"FF00"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => u4_countd_5_Q,
      O => u4_countd_5_rt
    );
  u4_n0010_4_XUSED : X_BUF
    port map (
      I => u4_n0010_4_Q,
      O => u4_n0010_4_0
    );
  u4_n0010_4_YUSED : X_BUF
    port map (
      I => u4_n0010_5_Q,
      O => u4_n0010_5_0
    );
  u4_clkdiv2_n0010_5_xor : X_XOR2
    port map (
      I0 => u4_clkdiv2_n0010_4_cyo,
      I1 => u4_countd_5_rt,
      O => u4_n0010_5_Q
    );
  u4_n0010_4_CYINIT_29 : X_BUF
    port map (
      I => u4_n0010_2_CYMUXG,
      O => u4_n0010_4_CYINIT
    );
  u6_countb_0_LOGIC_ZERO_30 : X_ZERO
    port map (
      O => u6_countb_0_LOGIC_ZERO
    );
  u6_clkdiv3_countb_n0000_0_cy : X_MUX2
    port map (
      IA => GLOBAL_LOGIC1,
      IB => u6_countb_0_LOGIC_ZERO,
      SEL => u6_N8,
      O => u6_clkdiv3_countb_n0000_0_cyo
    );
  u6_clkdiv3_countb_n0000_0_lut_INV_0 : X_LUT4
    generic map(
      INIT => X"00FF"
    )
    port map (
      ADR0 => GLOBAL_LOGIC1,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => u6_countb_0_Q,
      O => u6_N8
    );
  u6_countb_0_G : X_LUT4
    generic map(
      INIT => X"CCCC"
    )
    port map (
      ADR0 => GLOBAL_LOGIC0,
      ADR1 => u6_countb_1_Q,
      ADR2 => VCC,
      ADR3 => VCC,
      O => u6_countb_0_GROM
    );
  u6_clkdiv3_countb_n0000_1_cy : X_MUX2
    port map (
      IA => GLOBAL_LOGIC0,
      IB => u6_clkdiv3_countb_n0000_0_cyo,
      SEL => u6_countb_0_GROM,
      O => u6_countb_0_CYMUXG
    );
  u6_clkdiv3_countb_n0000_1_xor : X_XOR2
    port map (
      I0 => u6_clkdiv3_countb_n0000_0_cyo,
      I1 => u6_countb_0_GROM,
      O => u6_countb_n0000_1_Q
    );
  u6_countb_2_LOGIC_ZERO_31 : X_ZERO
    port map (
      O => u6_countb_2_LOGIC_ZERO
    );
  u6_clkdiv3_countb_n0000_2_cy : X_MUX2
    port map (
      IA => u6_countb_2_LOGIC_ZERO,
      IB => u6_countb_2_CYINIT,
      SEL => u6_countb_2_FROM,
      O => u6_clkdiv3_countb_n0000_2_cyo
    );
  u6_clkdiv3_countb_n0000_2_xor : X_XOR2
    port map (
      I0 => u6_countb_2_CYINIT,
      I1 => u6_countb_2_FROM,
      O => u6_countb_n0000_2_Q
    );
  u6_countb_2_F : X_LUT4
    generic map(
      INIT => X"FF00"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => u6_countb_2_Q,
      O => u6_countb_2_FROM
    );
  u6_countb_2_G : X_LUT4
    generic map(
      INIT => X"CCCC"
    )
    port map (
      ADR0 => VCC,
      ADR1 => u6_countb_3_Q,
      ADR2 => VCC,
      ADR3 => VCC,
      O => u6_countb_2_GROM
    );
  u6_clkdiv3_countb_n0000_3_cy : X_MUX2
    port map (
      IA => u6_countb_2_LOGIC_ZERO,
      IB => u6_clkdiv3_countb_n0000_2_cyo,
      SEL => u6_countb_2_GROM,
      O => u6_countb_2_CYMUXG
    );
  u6_clkdiv3_countb_n0000_3_xor : X_XOR2
    port map (
      I0 => u6_clkdiv3_countb_n0000_2_cyo,
      I1 => u6_countb_2_GROM,
      O => u6_countb_n0000_3_Q
    );
  u6_countb_2_CYINIT_32 : X_BUF
    port map (
      I => u6_countb_0_CYMUXG,
      O => u6_countb_2_CYINIT
    );
  u6_countb_2 : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => u6_countb_n0000_2_Q,
      CE => u6_n0005_0,
      CLK => Clk_BUFGP,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => u6_n0006_0,
      O => u6_countb_2_Q
    );
  u6_clkdiv3_countb_n0000_4_xor : X_XOR2
    port map (
      I0 => u6_countb_4_CYINIT,
      I1 => u6_countb_4_rt,
      O => u6_countb_n0000_4_Q
    );
  u6_countb_4_rt_33 : X_LUT4
    generic map(
      INIT => X"FF00"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => u6_countb_4_Q,
      O => u6_countb_4_rt
    );
  u6_countb_4_CYINIT_34 : X_BUF
    port map (
      I => u6_countb_2_CYMUXG,
      O => u6_countb_4_CYINIT
    );
  u6_countb_4 : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => u6_countb_n0000_4_Q,
      CE => u6_n0005_0,
      CLK => Clk_BUFGP,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => u6_n0006_0,
      O => u6_countb_4_Q
    );
  u4_n0009_1_LOGIC_ZERO_35 : X_ZERO
    port map (
      O => u4_n0009_1_LOGIC_ZERO
    );
  u4_clkdiv2_n0009_0_cy : X_MUX2
    port map (
      IA => GLOBAL_LOGIC1,
      IB => u4_n0009_1_LOGIC_ZERO,
      SEL => u4_N7,
      O => u4_clkdiv2_n0009_0_cyo
    );
  u4_clkdiv2_n0009_0_lut_INV_0 : X_LUT4
    generic map(
      INIT => X"00FF"
    )
    port map (
      ADR0 => GLOBAL_LOGIC1,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => u4_countc_0_Q,
      O => u4_N7
    );
  u4_n0009_1_G : X_LUT4
    generic map(
      INIT => X"F0F0"
    )
    port map (
      ADR0 => GLOBAL_LOGIC0,
      ADR1 => VCC,
      ADR2 => u4_countc_1_Q,
      ADR3 => VCC,
      O => u4_n0009_1_GROM
    );
  u4_n0009_1_YUSED : X_BUF
    port map (
      I => u4_n0009_1_Q,
      O => u4_n0009_1_0
    );
  u4_clkdiv2_n0009_1_cy : X_MUX2
    port map (
      IA => GLOBAL_LOGIC0,
      IB => u4_clkdiv2_n0009_0_cyo,
      SEL => u4_n0009_1_GROM,
      O => u4_n0009_1_CYMUXG
    );
  u4_clkdiv2_n0009_1_xor : X_XOR2
    port map (
      I0 => u4_clkdiv2_n0009_0_cyo,
      I1 => u4_n0009_1_GROM,
      O => u4_n0009_1_Q
    );
  u4_n0009_2_LOGIC_ZERO_36 : X_ZERO
    port map (
      O => u4_n0009_2_LOGIC_ZERO
    );
  u4_clkdiv2_n0009_2_cy : X_MUX2
    port map (
      IA => u4_n0009_2_LOGIC_ZERO,
      IB => u4_n0009_2_CYINIT,
      SEL => u4_n0009_2_FROM,
      O => u4_clkdiv2_n0009_2_cyo
    );
  u4_clkdiv2_n0009_2_xor : X_XOR2
    port map (
      I0 => u4_n0009_2_CYINIT,
      I1 => u4_n0009_2_FROM,
      O => u4_n0009_2_Q
    );
  u4_n0009_2_F : X_LUT4
    generic map(
      INIT => X"F0F0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => u4_countc_2_Q,
      ADR3 => VCC,
      O => u4_n0009_2_FROM
    );
  u4_n0009_2_G : X_LUT4
    generic map(
      INIT => X"FF00"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => u4_countc_3_Q,
      O => u4_n0009_2_GROM
    );
  u4_n0009_2_XUSED : X_BUF
    port map (
      I => u4_n0009_2_Q,
      O => u4_n0009_2_0
    );
  u4_n0009_2_YUSED : X_BUF
    port map (
      I => u4_n0009_3_Q,
      O => u4_n0009_3_0
    );
  u4_clkdiv2_n0009_3_cy : X_MUX2
    port map (
      IA => u4_n0009_2_LOGIC_ZERO,
      IB => u4_clkdiv2_n0009_2_cyo,
      SEL => u4_n0009_2_GROM,
      O => u4_n0009_2_CYMUXG
    );
  u4_clkdiv2_n0009_3_xor : X_XOR2
    port map (
      I0 => u4_clkdiv2_n0009_2_cyo,
      I1 => u4_n0009_2_GROM,
      O => u4_n0009_3_Q
    );
  u4_n0009_2_CYINIT_37 : X_BUF
    port map (
      I => u4_n0009_1_CYMUXG,
      O => u4_n0009_2_CYINIT
    );
  u4_n0009_4_LOGIC_ZERO_38 : X_ZERO
    port map (
      O => u4_n0009_4_LOGIC_ZERO
    );
  u4_clkdiv2_n0009_4_cy : X_MUX2
    port map (
      IA => u4_n0009_4_LOGIC_ZERO,
      IB => u4_n0009_4_CYINIT,
      SEL => u4_n0009_4_FROM,
      O => u4_clkdiv2_n0009_4_cyo
    );
  u4_clkdiv2_n0009_4_xor : X_XOR2
    port map (
      I0 => u4_n0009_4_CYINIT,
      I1 => u4_n0009_4_FROM,
      O => u4_n0009_4_Q
    );
  u4_n0009_4_F : X_LUT4
    generic map(
      INIT => X"F0F0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => u4_countc_4_Q,
      ADR3 => VCC,
      O => u4_n0009_4_FROM
    );
  u4_countc_5_rt_39 : X_LUT4
    generic map(
      INIT => X"FF00"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => u4_countc_5_Q,
      O => u4_countc_5_rt
    );
  u4_n0009_4_XUSED : X_BUF
    port map (
      I => u4_n0009_4_Q,
      O => u4_n0009_4_0
    );
  u4_n0009_4_YUSED : X_BUF
    port map (
      I => u4_n0009_5_Q,
      O => u4_n0009_5_0
    );
  u4_clkdiv2_n0009_5_xor : X_XOR2
    port map (
      I0 => u4_clkdiv2_n0009_4_cyo,
      I1 => u4_countc_5_rt,
      O => u4_n0009_5_Q
    );
  u4_n0009_4_CYINIT_40 : X_BUF
    port map (
      I => u4_n0009_2_CYMUXG,
      O => u4_n0009_4_CYINIT
    );
  u4_countb_0_LOGIC_ZERO_41 : X_ZERO
    port map (
      O => u4_countb_0_LOGIC_ZERO
    );
  u4_clkdiv2_countb_n0000_0_cy : X_MUX2
    port map (
      IA => GLOBAL_LOGIC1,
      IB => u4_countb_0_LOGIC_ZERO,
      SEL => u4_N8,
      O => u4_clkdiv2_countb_n0000_0_cyo
    );
  u4_clkdiv2_countb_n0000_0_lut_INV_0 : X_LUT4
    generic map(
      INIT => X"00FF"
    )
    port map (
      ADR0 => GLOBAL_LOGIC1,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => u4_countb_0_Q,
      O => u4_N8
    );
  u4_countb_0_G : X_LUT4
    generic map(
      INIT => X"FF00"
    )
    port map (
      ADR0 => GLOBAL_LOGIC0,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => u4_countb_1_Q,
      O => u4_countb_0_GROM
    );
  u4_clkdiv2_countb_n0000_1_cy : X_MUX2
    port map (
      IA => GLOBAL_LOGIC0,
      IB => u4_clkdiv2_countb_n0000_0_cyo,
      SEL => u4_countb_0_GROM,
      O => u4_countb_0_CYMUXG
    );
  u4_clkdiv2_countb_n0000_1_xor : X_XOR2
    port map (
      I0 => u4_clkdiv2_countb_n0000_0_cyo,
      I1 => u4_countb_0_GROM,
      O => u4_countb_n0000_1_Q
    );
  u4_countb_2_LOGIC_ZERO_42 : X_ZERO
    port map (
      O => u4_countb_2_LOGIC_ZERO
    );
  u4_clkdiv2_countb_n0000_2_cy : X_MUX2
    port map (
      IA => u4_countb_2_LOGIC_ZERO,
      IB => u4_countb_2_CYINIT,
      SEL => u4_countb_2_FROM,
      O => u4_clkdiv2_countb_n0000_2_cyo
    );
  u4_clkdiv2_countb_n0000_2_xor : X_XOR2
    port map (
      I0 => u4_countb_2_CYINIT,
      I1 => u4_countb_2_FROM,
      O => u4_countb_n0000_2_Q
    );
  u4_countb_2_F : X_LUT4
    generic map(
      INIT => X"F0F0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => u4_countb_2_Q,
      ADR3 => VCC,
      O => u4_countb_2_FROM
    );
  u4_countb_2_G : X_LUT4
    generic map(
      INIT =