microoven_timesim.vhd

微波爐．．．．．．．．．．．．．．．．．．．．．．．．．．

    generic map(
      INIT => X"F000"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => u1_EN,
      ADR3 => u3_n00051_O,
      O => u3_n0005
    );
  u3_n00051_O_XUSED : X_BUF
    port map (
      I => u3_n00051_O_pack_1,
      O => u3_n00051_O
    );
  u3_n00051_O_YUSED : X_BUF
    port map (
      I => u3_n0005,
      O => u3_n0005_0
    );
  u6_n0007_4_2 : X_LUT4
    generic map(
      INIT => X"0202"
    )
    port map (
      ADR0 => u6_n0009_4_0,
      ADR1 => u6_N29,
      ADR2 => u6_countb_0_Q,
      ADR3 => VCC,
      O => u6_n0007_4_2_O
    );
  u6_n0007_1_2 : X_LUT4
    generic map(
      INIT => X"0022"
    )
    port map (
      ADR0 => u6_n0009_1_0,
      ADR1 => u6_countb_0_Q,
      ADR2 => VCC,
      ADR3 => u6_N29,
      O => u6_n0007_1_2_O
    );
  u6_n0010_1_LOGIC_ZERO_9 : X_ZERO
    port map (
      O => u6_n0010_1_LOGIC_ZERO
    );
  u6_clkdiv3_n0010_0_cy : X_MUX2
    port map (
      IA => GLOBAL_LOGIC1,
      IB => u6_n0010_1_LOGIC_ZERO,
      SEL => u6_N6,
      O => u6_clkdiv3_n0010_0_cyo
    );
  u6_clkdiv3_n0010_0_lut_INV_0 : X_LUT4
    generic map(
      INIT => X"00FF"
    )
    port map (
      ADR0 => GLOBAL_LOGIC1,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => u6_countd_0_Q,
      O => u6_N6
    );
  u6_n0010_1_G : X_LUT4
    generic map(
      INIT => X"FF00"
    )
    port map (
      ADR0 => GLOBAL_LOGIC0,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => u6_countd_1_Q,
      O => u6_n0010_1_GROM
    );
  u6_n0010_1_YUSED : X_BUF
    port map (
      I => u6_n0010_1_Q,
      O => u6_n0010_1_0
    );
  u6_clkdiv3_n0010_1_cy : X_MUX2
    port map (
      IA => GLOBAL_LOGIC0,
      IB => u6_clkdiv3_n0010_0_cyo,
      SEL => u6_n0010_1_GROM,
      O => u6_n0010_1_CYMUXG
    );
  u6_clkdiv3_n0010_1_xor : X_XOR2
    port map (
      I0 => u6_clkdiv3_n0010_0_cyo,
      I1 => u6_n0010_1_GROM,
      O => u6_n0010_1_Q
    );
  u6_n0010_2_LOGIC_ZERO_10 : X_ZERO
    port map (
      O => u6_n0010_2_LOGIC_ZERO
    );
  u6_clkdiv3_n0010_2_cy : X_MUX2
    port map (
      IA => u6_n0010_2_LOGIC_ZERO,
      IB => u6_n0010_2_CYINIT,
      SEL => u6_n0010_2_FROM,
      O => u6_clkdiv3_n0010_2_cyo
    );
  u6_clkdiv3_n0010_2_xor : X_XOR2
    port map (
      I0 => u6_n0010_2_CYINIT,
      I1 => u6_n0010_2_FROM,
      O => u6_n0010_2_Q
    );
  u6_n0010_2_F : X_LUT4
    generic map(
      INIT => X"F0F0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => u6_countd_2_Q,
      ADR3 => VCC,
      O => u6_n0010_2_FROM
    );
  u6_n0010_2_G : X_LUT4
    generic map(
      INIT => X"FF00"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => u6_countd_3_Q,
      O => u6_n0010_2_GROM
    );
  u6_n0010_2_XUSED : X_BUF
    port map (
      I => u6_n0010_2_Q,
      O => u6_n0010_2_0
    );
  u6_n0010_2_YUSED : X_BUF
    port map (
      I => u6_n0010_3_Q,
      O => u6_n0010_3_0
    );
  u6_clkdiv3_n0010_3_cy : X_MUX2
    port map (
      IA => u6_n0010_2_LOGIC_ZERO,
      IB => u6_clkdiv3_n0010_2_cyo,
      SEL => u6_n0010_2_GROM,
      O => u6_n0010_2_CYMUXG
    );
  u6_clkdiv3_n0010_3_xor : X_XOR2
    port map (
      I0 => u6_clkdiv3_n0010_2_cyo,
      I1 => u6_n0010_2_GROM,
      O => u6_n0010_3_Q
    );
  u6_n0010_2_CYINIT_11 : X_BUF
    port map (
      I => u6_n0010_1_CYMUXG,
      O => u6_n0010_2_CYINIT
    );
  u6_clkdiv3_n0010_4_xor : X_XOR2
    port map (
      I0 => u6_n0010_4_CYINIT,
      I1 => u6_countd_4_rt,
      O => u6_n0010_4_Q
    );
  u6_countd_4_rt_12 : X_LUT4
    generic map(
      INIT => X"AAAA"
    )
    port map (
      ADR0 => u6_countd_4_Q,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => u6_countd_4_rt
    );
  u6_n0010_4_XUSED : X_BUF
    port map (
      I => u6_n0010_4_Q,
      O => u6_n0010_4_0
    );
  u6_n0010_4_CYINIT_13 : X_BUF
    port map (
      I => u6_n0010_2_CYMUXG,
      O => u6_n0010_4_CYINIT
    );
  u6_counta_0_LOGIC_ZERO_14 : X_ZERO
    port map (
      O => u6_counta_0_LOGIC_ZERO
    );
  u6_clkdiv3_counta_n0000_0_cy : X_MUX2
    port map (
      IA => GLOBAL_LOGIC1,
      IB => u6_counta_0_LOGIC_ZERO,
      SEL => u6_N9,
      O => u6_clkdiv3_counta_n0000_0_cyo
    );
  u6_clkdiv3_counta_n0000_0_lut_INV_0 : X_LUT4
    generic map(
      INIT => X"3333"
    )
    port map (
      ADR0 => GLOBAL_LOGIC1,
      ADR1 => u6_counta_0_Q,
      ADR2 => VCC,
      ADR3 => VCC,
      O => u6_N9
    );
  u6_counta_0_G : X_LUT4
    generic map(
      INIT => X"F0F0"
    )
    port map (
      ADR0 => GLOBAL_LOGIC0,
      ADR1 => VCC,
      ADR2 => u6_counta_1_Q,
      ADR3 => VCC,
      O => u6_counta_0_GROM
    );
  u6_clkdiv3_counta_n0000_1_cy : X_MUX2
    port map (
      IA => GLOBAL_LOGIC0,
      IB => u6_clkdiv3_counta_n0000_0_cyo,
      SEL => u6_counta_0_GROM,
      O => u6_counta_0_CYMUXG
    );
  u6_clkdiv3_counta_n0000_1_xor : X_XOR2
    port map (
      I0 => u6_clkdiv3_counta_n0000_0_cyo,
      I1 => u6_counta_0_GROM,
      O => u6_counta_n0000_1_Q
    );
  u6_counta_2_LOGIC_ZERO_15 : X_ZERO
    port map (
      O => u6_counta_2_LOGIC_ZERO
    );
  u6_clkdiv3_counta_n0000_2_cy : X_MUX2
    port map (
      IA => u6_counta_2_LOGIC_ZERO,
      IB => u6_counta_2_CYINIT,
      SEL => u6_counta_2_FROM,
      O => u6_clkdiv3_counta_n0000_2_cyo
    );
  u6_clkdiv3_counta_n0000_2_xor : X_XOR2
    port map (
      I0 => u6_counta_2_CYINIT,
      I1 => u6_counta_2_FROM,
      O => u6_counta_n0000_2_Q
    );
  u6_counta_2_F : X_LUT4
    generic map(
      INIT => X"FF00"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => u6_counta_2_Q,
      O => u6_counta_2_FROM
    );
  u6_counta_2_G : X_LUT4
    generic map(
      INIT => X"F0F0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => u6_counta_3_Q,
      ADR3 => VCC,
      O => u6_counta_2_GROM
    );
  u6_clkdiv3_counta_n0000_3_cy : X_MUX2
    port map (
      IA => u6_counta_2_LOGIC_ZERO,
      IB => u6_clkdiv3_counta_n0000_2_cyo,
      SEL => u6_counta_2_GROM,
      O => u6_counta_2_CYMUXG
    );
  u6_clkdiv3_counta_n0000_3_xor : X_XOR2
    port map (
      I0 => u6_clkdiv3_counta_n0000_2_cyo,
      I1 => u6_counta_2_GROM,
      O => u6_counta_n0000_3_Q
    );
  u6_counta_2_CYINIT_16 : X_BUF
    port map (
      I => u6_counta_0_CYMUXG,
      O => u6_counta_2_CYINIT
    );
  u6_counta_2 : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => u6_counta_n0000_2_Q,
      CE => VCC,
      CLK => Clk_BUFGP,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => u6_n0005_0,
      O => u6_counta_2_Q
    );
  u6_clkdiv3_counta_n0000_4_xor : X_XOR2
    port map (
      I0 => u6_counta_4_CYINIT,
      I1 => u6_counta_4_rt,
      O => u6_counta_n0000_4_Q
    );
  u6_counta_4_rt_17 : X_LUT4
    generic map(
      INIT => X"FF00"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => u6_counta_4_Q,
      O => u6_counta_4_rt
    );
  u6_counta_4_CYINIT_18 : X_BUF
    port map (
      I => u6_counta_2_CYMUXG,
      O => u6_counta_4_CYINIT
    );
  u6_counta_4 : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => u6_counta_n0000_4_Q,
      CE => VCC,
      CLK => Clk_BUFGP,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => u6_n0005_0,
      O => u6_counta_4_Q
    );
  u6_n0009_1_LOGIC_ZERO_19 : X_ZERO
    port map (
      O => u6_n0009_1_LOGIC_ZERO
    );
  u6_clkdiv3_n0009_0_cy : X_MUX2
    port map (
      IA => GLOBAL_LOGIC1,
      IB => u6_n0009_1_LOGIC_ZERO,
      SEL => u6_N7,
      O => u6_clkdiv3_n0009_0_cyo
    );
  u6_clkdiv3_n0009_0_lut_INV_0 : X_LUT4
    generic map(
      INIT => X"0F0F"
    )
    port map (
      ADR0 => GLOBAL_LOGIC1,
      ADR1 => VCC,
      ADR2 => u6_countc_0_Q,
      ADR3 => VCC,
      O => u6_N7
    );
  u6_n0009_1_G : X_LUT4
    generic map(
      INIT => X"FF00"
    )
    port map (
      ADR0 => GLOBAL_LOGIC0,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => u6_countc_1_Q,
      O => u6_n0009_1_GROM
    );
  u6_n0009_1_YUSED : X_BUF
    port map (
      I => u6_n0009_1_Q,
      O => u6_n0009_1_0
    );
  u6_clkdiv3_n0009_1_cy : X_MUX2
    port map (
      IA => GLOBAL_LOGIC0,
      IB => u6_clkdiv3_n0009_0_cyo,
      SEL => u6_n0009_1_GROM,
      O => u6_n0009_1_CYMUXG
    );
  u6_clkdiv3_n0009_1_xor : X_XOR2
    port map (
      I0 => u6_clkdiv3_n0009_0_cyo,
      I1 => u6_n0009_1_GROM,
      O => u6_n0009_1_Q
    );
  u6_n0009_2_LOGIC_ZERO_20 : X_ZERO
    port map (
      O => u6_n0009_2_LOGIC_ZERO
    );
  u6_clkdiv3_n0009_2_cy : X_MUX2
    port map (
      IA => u6_n0009_2_LOGIC_ZERO,
      IB => u6_n0009_2_CYINIT,
      SEL => u6_n0009_2_FROM,
      O => u6_clkdiv3_n0009_2_cyo
    );
  u6_clkdiv3_n0009_2_xor : X_XOR2
    port map (
      I0 => u6_n0009_2_CYINIT,
      I1 => u6_n0009_2_FROM,
      O => u6_n0009_2_Q
    );
  u6_n0009_2_F : X_LUT4
    generic map(
      INIT => X"CCCC"
    )
    port map (
      ADR0 => VCC,
      ADR1 => u6_countc_2_Q,
      ADR2 => VCC,
      ADR3 => VCC,
      O => u6_n0009_2_FROM
    );
  u6_n0009_2_G : X_LUT4
    generic map(
      INIT => X"F0F0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => u6_countc_3_Q,
      ADR3 => VCC,
      O => u6_n0009_2_GROM
    );
  u6_n0009_2_XUSED : X_BUF
    port map (
      I => u6_n0009_2_Q,
      O => u6_n0009_2_0
    );
  u6_n0009_2_YUSED : X_BUF
    port map (
      I => u6_n0009_3_Q,
      O => u6_n0009_3_0
    );
  u6_clkdiv3_n0009_3_cy : X_MUX2
    port map (
      IA => u6_n0009_2_LOGIC_ZERO,
      IB => u6_clkdiv3_n0009_2_cyo,
      SEL => u6_n0009_2_GROM,
      O => u6_n0009_2_CYMUXG
    );
  u6_clkdiv3_n0009_3_xor : X_XOR2
    port map (
      I0 => u6_clkdiv3_n0009_2_cyo,
      I1 => u6_n0009_2_GROM,
      O => u6_n0009_3_Q
    );
  u6_n0009_2_CYINIT_21 : X_BUF
    port map (
      I => u6_n0009_1_CYMUXG,
      O => u6_n0009_2_CYINIT
    );
  u6_clkdiv3_n0009_4_xor : X_XOR2
    port map (
      I0 => u6_n0009_4_CYINIT,
      I1 => u6_countc_4_rt,
      O => u6_n0009_4_Q
    );
  u6_countc_4_rt_22 : X_LUT4
    generic map(
      INIT => X"FF00"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => u6_countc_4_Q,
      O => u6_countc_4_rt
    );
  u6_n0009_4_XUSED : X_BUF
    port map (
      I => u6_n0009_4_Q,
      O => u6_n0009_4_0
    );
  u6_n0009_4_CYINIT_23 : X_BUF
    port map (
      I => u6_n0009_2_CYMUXG,
      O => u6_n0009_4_CYINIT
    );
  u4_counta_0_LOGIC_ZERO_24 : X_ZERO
    port map (
      O => u4_counta_0_LOGIC_ZERO
    );
  u4_clkdiv2_counta_n0000_0_cy : X_MUX2
    port map (
      IA => GLOBAL_LOGIC1,
      IB => u4_counta_0_LOGIC_ZERO,
      SEL => u4_N9,
      O => u4_clkdiv2_counta_n0000_0_cyo
    );
  u4_clkdiv2_counta_n0000_0_lut_INV_0 : X_LUT4
    generic map(
      INIT => X"3333"
    )
    port map (
      ADR0 => GLOBAL_LOGIC1,
      ADR1 => u4_counta_0_Q,
      ADR2 => VCC,
      ADR3 => VCC,
      O => u4_N9
    );
  u4_counta_0_G : X_LUT4
    generic map(
      INIT => X"FF00"
    )
    port map (
      ADR0 => GLOBAL_LOGIC0,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => u4_counta_1_Q,
      O => u4_counta_0_GROM
    );
  u4_clkdiv2_counta_n0000_1_cy : X_MUX2
    port map (
      IA => GLOBAL_LOGIC0,
      IB => u4_clkdiv2_counta_n0000_0_cyo,
      SEL => u4_counta_0_GROM,
      O => u4_counta_0_CYMUXG
    );
  u4_clkdiv2_counta_n0000_1_xor : X_XOR2
    port map (
      I0 => u4_clkdiv2_counta_n0000_0_cyo,
      I1 => u4_counta_0_GROM,
      O => u4_counta_n0000_1_Q
    );
  u4_counta_2 : X_SFF
    generic map(
      INIT => '0'
    )
    port map (