microoven_timesim.vhd

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      O => u6_n0022_0
    );
  u1_n00021 : X_LUT4
    generic map(
      INIT => X"0F00"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => u1_EN,
      ADR3 => Clear_IBUF_0,
      O => u1_n0002
    );
  u1_EN_ClkEn_INV1 : X_LUT4
    generic map(
      INIT => X"5F5F"
    )
    port map (
      ADR0 => Clear_IBUF_0,
      ADR1 => VCC,
      ADR2 => Start_IBUF_0,
      ADR3 => VCC,
      O => u1_EN_N1_pack_1
    );
  u1_EN_YUSED : X_BUF
    port map (
      I => u1_EN_N1_pack_1,
      O => u1_EN_N1
    );
  u1_EN_SRMUX : X_INV
    port map (
      I => Door_IBUF,
      O => u1_EN_SRMUX_OUTPUTNOT
    );
  u5_Mrom_output_inst_lut4_51 : X_LUT4
    generic map(
      INIT => X"E448"
    )
    port map (
      ADR0 => u3_COUNT_0_Q,
      ADR1 => u3_COUNT_2_Q,
      ADR2 => u3_COUNT_3_Q,
      ADR3 => u3_COUNT_1_Q,
      O => f_OBUF
    );
  u5_Mrom_output_inst_lut4_01 : X_LUT4
    generic map(
      INIT => X"0483"
    )
    port map (
      ADR0 => u3_COUNT_0_Q,
      ADR1 => u3_COUNT_2_Q,
      ADR2 => u3_COUNT_1_Q,
      ADR3 => u3_COUNT_3_Q,
      O => a_OBUF
    );
  u4_counta_4_LOGIC_ZERO_1 : X_ZERO
    port map (
      O => u4_counta_4_LOGIC_ZERO
    );
  u4_clkdiv2_counta_n0000_4_cy : X_MUX2
    port map (
      IA => u4_counta_4_LOGIC_ZERO,
      IB => u4_counta_4_CYINIT,
      SEL => u4_counta_4_FROM,
      O => u4_clkdiv2_counta_n0000_4_cyo
    );
  u4_clkdiv2_counta_n0000_4_xor : X_XOR2
    port map (
      I0 => u4_counta_4_CYINIT,
      I1 => u4_counta_4_FROM,
      O => u4_counta_n0000_4_Q
    );
  u4_counta_4_F : X_LUT4
    generic map(
      INIT => X"FF00"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => u4_counta_4_Q,
      O => u4_counta_4_FROM
    );
  u4_counta_5_rt_2 : X_LUT4
    generic map(
      INIT => X"FF00"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => u4_counta_5_Q,
      O => u4_counta_5_rt
    );
  u4_clkdiv2_counta_n0000_5_xor : X_XOR2
    port map (
      I0 => u4_clkdiv2_counta_n0000_4_cyo,
      I1 => u4_counta_5_rt,
      O => u4_counta_n0000_5_Q
    );
  u4_counta_4_CYINIT_3 : X_BUF
    port map (
      I => u4_counta_2_CYMUXG,
      O => u4_counta_4_CYINIT
    );
  u4_counta_4 : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => u4_counta_n0000_4_Q,
      CE => VCC,
      CLK => Clk_BUFGP,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => u4_n0005_0,
      O => u4_counta_4_Q
    );
  u3_COUNT_n0001_2_SW0 : X_LUT4
    generic map(
      INIT => X"FFAA"
    )
    port map (
      ADR0 => u3_COUNT_0_Q,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => u3_COUNT_1_Q,
      O => u3_COUNT_n0001_2_SW0_O_pack_1
    );
  u3_COUNT_n0001_2_Q : X_LUT4
    generic map(
      INIT => X"ACA3"
    )
    port map (
      ADR0 => u2_Qn_2_Q,
      ADR1 => u3_COUNT_2_Q,
      ADR2 => u2_kload,
      ADR3 => u3_COUNT_n0001_2_SW0_O,
      O => u3_COUNT_n0001_2_O
    );
  u3_COUNT_2_XUSED : X_BUF
    port map (
      I => u3_COUNT_n0001_2_SW0_O_pack_1,
      O => u3_COUNT_n0001_2_SW0_O
    );
  u3_COUNT_2 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => u3_COUNT_n0001_2_O,
      CE => u3_n0005_0,
      CLK => u4_B,
      SET => u3_COUNT_2_FFY_SET,
      RST => u3_COUNT_2_FFY_RST,
      O => u3_COUNT_2_Q
    );
  u3_COUNT_2_FFY_SETOR : X_BUF
    port map (
      I => u3_COUNT_0_2_n0001,
      O => u3_COUNT_2_FFY_SET
    );
  u3_COUNT_2_FFY_RSTOR : X_OR2
    port map (
      I0 => u3_COUNT_0_2_n0000_0,
      I1 => GSR,
      O => u3_COUNT_2_FFY_RST
    );
  u3_COUNT_n0001_3_SW0 : X_LUT4
    generic map(
      INIT => X"FFEE"
    )
    port map (
      ADR0 => u3_COUNT_1_Q,
      ADR1 => u3_COUNT_2_Q,
      ADR2 => VCC,
      ADR3 => u3_COUNT_0_Q,
      O => u3_COUNT_n0001_3_SW0_O_pack_1
    );
  u3_COUNT_n0001_3_Q : X_LUT4
    generic map(
      INIT => X"E4B1"
    )
    port map (
      ADR0 => u2_kload,
      ADR1 => u3_COUNT_3_Q,
      ADR2 => u2_Qn_3_Q,
      ADR3 => u3_COUNT_n0001_3_SW0_O,
      O => u3_COUNT_n0001_3_O
    );
  u3_COUNT_3_XUSED : X_BUF
    port map (
      I => u3_COUNT_n0001_3_SW0_O_pack_1,
      O => u3_COUNT_n0001_3_SW0_O
    );
  u3_COUNT_3 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => u3_COUNT_n0001_3_O,
      CE => u3_n0005_0,
      CLK => u4_B,
      SET => u3_COUNT_3_FFY_SET,
      RST => u3_COUNT_3_FFY_RST,
      O => u3_COUNT_3_Q
    );
  u3_COUNT_3_FFY_SETOR : X_BUF
    port map (
      I => u3_COUNT_0_3_n0001,
      O => u3_COUNT_3_FFY_SET
    );
  u3_COUNT_3_FFY_RSTOR : X_OR2
    port map (
      I0 => u3_COUNT_0_3_n0000_0,
      I1 => GSR,
      O => u3_COUNT_3_FFY_RST
    );
  u4_n0021_4 : X_LUT4
    generic map(
      INIT => X"0002"
    )
    port map (
      ADR0 => u4_countd_1_Q,
      ADR1 => u4_countd_0_Q,
      ADR2 => u4_countd_2_Q,
      ADR3 => N216_0,
      O => u4_n0021_pack_1
    );
  u4_n00251 : X_LUT4
    generic map(
      INIT => X"0302"
    )
    port map (
      ADR0 => u4_n0012_0,
      ADR1 => u4_n0011_0,
      ADR2 => u4_n0005_0,
      ADR3 => u4_n0021,
      O => u4_n0025
    );
  u4_n0021_XUSED : X_BUF
    port map (
      I => u4_n0021_pack_1,
      O => u4_n0021
    );
  u4_n0021_YUSED : X_BUF
    port map (
      I => u4_n0025,
      O => u4_n0025_0
    );
  u6_n0011_SW0 : X_LUT4
    generic map(
      INIT => X"F000"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => u6_countb_4_Q,
      ADR3 => u6_countb_3_Q,
      O => u6_n0011_SW0_O_pack_1
    );
  u6_n0011_5 : X_LUT4
    generic map(
      INIT => X"1000"
    )
    port map (
      ADR0 => u6_countb_1_Q,
      ADR1 => u6_countb_0_Q,
      ADR2 => u6_countb_2_Q,
      ADR3 => u6_n0011_SW0_O,
      O => u6_n0011
    );
  u6_n0011_SW0_O_XUSED : X_BUF
    port map (
      I => u6_n0011_SW0_O_pack_1,
      O => u6_n0011_SW0_O
    );
  u6_n0011_SW0_O_YUSED : X_BUF
    port map (
      I => u6_n0011,
      O => u6_n0011_0
    );
  u6_n0005_SW0 : X_LUT4
    generic map(
      INIT => X"A0A0"
    )
    port map (
      ADR0 => u6_counta_4_Q,
      ADR1 => VCC,
      ADR2 => u6_counta_3_Q,
      ADR3 => VCC,
      O => u6_n0005_SW0_O_pack_1
    );
  u6_n0005_6 : X_LUT4
    generic map(
      INIT => X"0400"
    )
    port map (
      ADR0 => u6_counta_0_Q,
      ADR1 => u6_counta_2_Q,
      ADR2 => u6_counta_1_Q,
      ADR3 => u6_n0005_SW0_O,
      O => u6_n0005
    );
  u6_n0005_SW0_O_XUSED : X_BUF
    port map (
      I => u6_n0005_SW0_O_pack_1,
      O => u6_n0005_SW0_O
    );
  u6_n0005_SW0_O_YUSED : X_BUF
    port map (
      I => u6_n0005,
      O => u6_n0005_0
    );
  u6_n0021_SW0 : X_LUT4
    generic map(
      INIT => X"AA00"
    )
    port map (
      ADR0 => u6_countd_4_Q,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => u6_countd_3_Q,
      O => u6_n0021_SW0_O_pack_1
    );
  u6_n0021_7 : X_LUT4
    generic map(
      INIT => X"0400"
    )
    port map (
      ADR0 => u6_countd_1_Q,
      ADR1 => u6_countd_2_Q,
      ADR2 => u6_countd_0_Q,
      ADR3 => u6_n0021_SW0_O,
      O => u6_n0021
    );
  u6_n0021_SW0_O_XUSED : X_BUF
    port map (
      I => u6_n0021_SW0_O_pack_1,
      O => u6_n0021_SW0_O
    );
  u6_n0021_SW0_O_YUSED : X_BUF
    port map (
      I => u6_n0021,
      O => u6_n0021_0
    );
  u6_n0012_8 : X_LUT4
    generic map(
      INIT => X"0008"
    )
    port map (
      ADR0 => u6_countc_2_Q,
      ADR1 => N210_0,
      ADR2 => u6_countc_1_Q,
      ADR3 => u6_countc_0_Q,
      O => u6_n0012_pack_1
    );
  u6_n00251 : X_LUT4
    generic map(
      INIT => X"0504"
    )
    port map (
      ADR0 => u6_n0011_0,
      ADR1 => u6_n0021_0,
      ADR2 => u6_n0005_0,
      ADR3 => u6_n0012,
      O => u6_n0025
    );
  u6_n0012_XUSED : X_BUF
    port map (
      I => u6_n0012_pack_1,
      O => u6_n0012
    );
  u6_n0012_YUSED : X_BUF
    port map (
      I => u6_n0025,
      O => u6_n0025_0
    );
  u4_n0007_1_2 : X_LUT4
    generic map(
      INIT => X"0200"
    )
    port map (
      ADR0 => u4_n0009_1_0,
      ADR1 => u4_countb_0_Q,
      ADR2 => u4_N33,
      ADR3 => u4_countb_1_Q,
      O => u4_n0007_1_2_O
    );
  u4_countc_1 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => u4_n0007_1_2_O,
      CE => u4_n0024_0,
      CLK => Clk_BUFGP,
      SET => GND,
      RST => u4_countc_1_FFY_RST,
      O => u4_countc_1_Q
    );
  u4_countc_1_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => u4_countc_1_FFY_RST
    );
  u4_n0007_3_2 : X_LUT4
    generic map(
      INIT => X"0400"
    )
    port map (
      ADR0 => u4_N33,
      ADR1 => u4_n0009_3_0,
      ADR2 => u4_countb_0_Q,
      ADR3 => u4_countb_1_Q,
      O => u4_n0007_3_2_O
    );
  u4_n0007_2_2 : X_LUT4
    generic map(
      INIT => X"0200"
    )
    port map (
      ADR0 => u4_n0009_2_0,
      ADR1 => u4_N33,
      ADR2 => u4_countb_0_Q,
      ADR3 => u4_countb_1_Q,
      O => u4_n0007_2_2_O
    );
  u4_n0007_5_2 : X_LUT4
    generic map(
      INIT => X"0400"
    )
    port map (
      ADR0 => u4_N33,
      ADR1 => u4_n0009_5_0,
      ADR2 => u4_countb_0_Q,
      ADR3 => u4_countb_1_Q,
      O => u4_n0007_5_2_O
    );
  u4_n0007_4_2 : X_LUT4
    generic map(
      INIT => X"0200"
    )
    port map (
      ADR0 => u4_n0009_4_0,
      ADR1 => u4_countb_0_Q,
      ADR2 => u4_N33,
      ADR3 => u4_countb_1_Q,
      O => u4_n0007_4_2_O
    );
  u4_n0008_1_2 : X_LUT4
    generic map(
      INIT => X"0020"
    )
    port map (
      ADR0 => u4_countc_1_Q,
      ADR1 => u4_countc_0_Q,
      ADR2 => u4_n0010_1_0,
      ADR3 => u4_N19,
      O => u4_n0008_1_2_O
    );
  u4_countd_1 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => u4_n0008_1_2_O,
      CE => u4_n0025_0,
      CLK => Clk_BUFGP,
      SET => GND,
      RST => u4_countd_1_FFY_RST,
      O => u4_countd_1_Q
    );
  u4_countd_1_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => u4_countd_1_FFY_RST
    );
  u4_n0008_3_2 : X_LUT4
    generic map(
      INIT => X"0400"
    )
    port map (
      ADR0 => u4_countc_0_Q,
      ADR1 => u4_n0010_3_0,
      ADR2 => u4_N19,
      ADR3 => u4_countc_1_Q,
      O => u4_n0008_3_2_O
    );
  u4_n0008_2_2 : X_LUT4
    generic map(
      INIT => X"0020"
    )
    port map (
      ADR0 => u4_n0010_2_0,
      ADR1 => u4_N19,
      ADR2 => u4_countc_1_Q,
      ADR3 => u4_countc_0_Q,
      O => u4_n0008_2_2_O
    );
  u4_n0008_5_2 : X_LUT4
    generic map(
      INIT => X"0400"
    )
    port map (
      ADR0 => u4_countc_0_Q,
      ADR1 => u4_n0010_5_0,
      ADR2 => u4_N19,
      ADR3 => u4_countc_1_Q,
      O => u4_n0008_5_2_O
    );
  u4_n0008_4_2 : X_LUT4
    generic map(
      INIT => X"0008"
    )
    port map (
      ADR0 => u4_n0010_4_0,
      ADR1 => u4_countc_1_Q,
      ADR2 => u4_N19,
      ADR3 => u4_countc_0_Q,
      O => u4_n0008_4_2_O
    );
  u3_n00051 : X_LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      ADR0 => u3_COUNT_3_Q,
      ADR1 => u3_COUNT_0_Q,
      ADR2 => u3_COUNT_1_Q,
      ADR3 => u3_COUNT_2_Q,
      O => u3_n00051_O_pack_1
    );
  u3_n00052 : X_LUT4