microoven_timesim.vhd

微波爐．．．．．．．．．．．．．．．．．．．．．．．．．．

  signal u4_countc_3_FFX_RST : STD_LOGIC; 
  signal u4_countc_5_FFX_RST : STD_LOGIC; 
  signal u4_countd_3_FFX_RST : STD_LOGIC; 
  signal u4_countd_5_FFX_RST : STD_LOGIC; 
  signal u6_countc_4_FFX_RST : STD_LOGIC; 
  signal u6_countc_3_FFX_RST : STD_LOGIC; 
  signal VCC : STD_LOGIC; 
  signal GND : STD_LOGIC; 
begin
  u2_n0002_3_1 : X_LUT4
    generic map(
      INIT => X"2800"
    )
    port map (
      ADR0 => u2_N14,
      ADR1 => key9_IBUF_0,
      ADR2 => key8_IBUF_0,
      ADR3 => u2_N16_0,
      O => u2_n0002_3_Q
    );
  u2_n0002_2_Q_0 : X_LUT4
    generic map(
      INIT => X"0100"
    )
    port map (
      ADR0 => key2_IBUF_0,
      ADR1 => N6_0,
      ADR2 => key3_IBUF_0,
      ADR3 => u2_N15,
      O => u2_n0002_2_Q
    );
  u3_COUNT_0_n00011 : X_LUT4
    generic map(
      INIT => X"F000"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => u2_kload,
      ADR3 => u2_Qn_0_Q,
      O => u3_COUNT_0_0_n0001_pack_1
    );
  u3_COUNT_n0001_0_1 : X_LUT4
    generic map(
      INIT => X"C5C5"
    )
    port map (
      ADR0 => u3_COUNT_0_Q,
      ADR1 => u2_Qn_0_Q,
      ADR2 => u2_kload,
      ADR3 => VCC,
      O => u3_COUNT_n0001_0_Q
    );
  u3_COUNT_0 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => u3_COUNT_n0001_0_Q,
      CE => u3_n0005_0,
      CLK => u4_B,
      SET => u3_COUNT_0_FFY_SET,
      RST => u3_COUNT_0_FFY_RST,
      O => u3_COUNT_0_Q
    );
  u3_COUNT_0_FFY_SETOR : X_BUF
    port map (
      I => u3_COUNT_0_0_n0001_pack_1,
      O => u3_COUNT_0_FFY_SET
    );
  u3_COUNT_0_FFY_RSTOR : X_OR2
    port map (
      I0 => u3_COUNT_0_0_n0000_0,
      I1 => GSR,
      O => u3_COUNT_0_FFY_RST
    );
  u3_COUNT_1_n00011 : X_LUT4
    generic map(
      INIT => X"AA00"
    )
    port map (
      ADR0 => u2_kload,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => u2_Qn_1_Q,
      O => u3_COUNT_0_1_n0001_pack_1
    );
  u3_COUNT_n0001_1_1 : X_LUT4
    generic map(
      INIT => X"B88B"
    )
    port map (
      ADR0 => u2_Qn_1_Q,
      ADR1 => u2_kload,
      ADR2 => u3_COUNT_0_Q,
      ADR3 => u3_COUNT_1_Q,
      O => u3_COUNT_n0001_1_Q
    );
  u3_COUNT_1 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => u3_COUNT_n0001_1_Q,
      CE => u3_n0005_0,
      CLK => u4_B,
      SET => u3_COUNT_1_FFY_SET,
      RST => u3_COUNT_1_FFY_RST,
      O => u3_COUNT_1_Q
    );
  u3_COUNT_1_FFY_SETOR : X_BUF
    port map (
      I => u3_COUNT_0_1_n0001_pack_1,
      O => u3_COUNT_1_FFY_SET
    );
  u3_COUNT_1_FFY_RSTOR : X_OR2
    port map (
      I0 => u3_COUNT_0_1_n0000_0,
      I1 => GSR,
      O => u3_COUNT_1_FFY_RST
    );
  u1_n0003_1_1 : X_LUT4
    generic map(
      INIT => X"E0F6"
    )
    port map (
      ADR0 => key9_IBUF_0,
      ADR1 => key7_IBUF_0,
      ADR2 => u1_temp_LED_1_Q,
      ADR3 => key8_IBUF_0,
      O => u1_n0003_1_Q
    );
  u1_n0003_0_1 : X_LUT4
    generic map(
      INIT => X"F1D4"
    )
    port map (
      ADR0 => key7_IBUF_0,
      ADR1 => key9_IBUF_0,
      ADR2 => u1_temp_LED_0_Q,
      ADR3 => key8_IBUF_0,
      O => u1_n0003_0_Q
    );
  u1_temp_LED_1_CEMUX : X_INV
    port map (
      I => Set_IBUF_0,
      O => u1_temp_LED_1_CEMUXNOT
    );
  u1_temp_LED_1_SRMUX : X_INV
    port map (
      I => Clear_IBUF_0,
      O => u1_temp_LED_1_SRMUX_OUTPUTNOT
    );
  u2_n0002_2_SW0 : X_LUT4
    generic map(
      INIT => X"FEE9"
    )
    port map (
      ADR0 => key7_IBUF_0,
      ADR1 => key6_IBUF_0,
      ADR2 => key5_IBUF_0,
      ADR3 => key4_IBUF_0,
      O => N6
    );
  u1_n0003_2_1 : X_LUT4
    generic map(
      INIT => X"F1B2"
    )
    port map (
      ADR0 => key7_IBUF_0,
      ADR1 => key9_IBUF_0,
      ADR2 => u1_temp_LED_2_Q,
      ADR3 => key8_IBUF_0,
      O => u1_n0003_2_Q
    );
  u1_temp_LED_2_CEMUX : X_INV
    port map (
      I => Set_IBUF_0,
      O => u1_temp_LED_2_CEMUXNOT
    );
  u1_temp_LED_2_XUSED : X_BUF
    port map (
      I => N6,
      O => N6_0
    );
  u1_temp_LED_2_SRMUX : X_INV
    port map (
      I => Clear_IBUF_0,
      O => u1_temp_LED_2_SRMUX_OUTPUTNOT
    );
  u1_temp_LED_2 : X_SFF
    generic map(
      INIT => '1'
    )
    port map (
      I => u1_n0003_2_Q,
      CE => u1_temp_LED_2_CEMUXNOT,
      CLK => u6_B,
      SET => GSR,
      RST => GND,
      SSET => u1_temp_LED_2_SRMUX_OUTPUTNOT,
      SRST => GND,
      O => u1_temp_LED_2_Q
    );
  u4_n0008_4_1 : X_LUT4
    generic map(
      INIT => X"FBFF"
    )
    port map (
      ADR0 => u4_countc_3_Q,
      ADR1 => u4_countc_5_Q,
      ADR2 => u4_countc_2_Q,
      ADR3 => u4_countc_4_Q,
      O => u4_N19_pack_1
    );
  u4_n0008_0_2 : X_LUT4
    generic map(
      INIT => X"0004"
    )
    port map (
      ADR0 => u4_countd_0_Q,
      ADR1 => u4_countc_1_Q,
      ADR2 => u4_countc_0_Q,
      ADR3 => u4_N19,
      O => u4_n0008_0_Q
    );
  u4_countd_0_XUSED : X_BUF
    port map (
      I => u4_N19_pack_1,
      O => u4_N19
    );
  u4_countd_0 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => u4_n0008_0_Q,
      CE => u4_n0025_0,
      CLK => Clk_BUFGP,
      SET => GND,
      RST => u4_countd_0_FFY_RST,
      O => u4_countd_0_Q
    );
  u4_countd_0_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => u4_countd_0_FFY_RST
    );
  u4_n0021_SW0 : X_LUT4
    generic map(
      INIT => X"F5FF"
    )
    port map (
      ADR0 => u4_countd_5_Q,
      ADR1 => VCC,
      ADR2 => u4_countd_3_Q,
      ADR3 => u4_countd_4_Q,
      O => N216
    );
  N216_YUSED : X_BUF
    port map (
      I => N216,
      O => N216_0
    );
  u2_n0002_1_SW0 : X_LUT4
    generic map(
      INIT => X"FEE9"
    )
    port map (
      ADR0 => key6_IBUF_0,
      ADR1 => key7_IBUF_0,
      ADR2 => key2_IBUF_0,
      ADR3 => key3_IBUF_0,
      O => N4
    );
  u2_n000554 : X_LUT4
    generic map(
      INIT => X"0112"
    )
    port map (
      ADR0 => key0_IBUF_0,
      ADR1 => key6_IBUF_0,
      ADR2 => key2_IBUF_0,
      ADR3 => key8_IBUF_0,
      O => CHOICE688
    );
  N4_XUSED : X_BUF
    port map (
      I => N4,
      O => N4_0
    );
  N4_YUSED : X_BUF
    port map (
      I => CHOICE688,
      O => CHOICE688_0
    );
  u2_n000593 : X_LUT4
    generic map(
      INIT => X"050A"
    )
    port map (
      ADR0 => key6_IBUF_0,
      ADR1 => VCC,
      ADR2 => key8_IBUF_0,
      ADR3 => key4_IBUF_0,
      O => CHOICE699_pack_1
    );
  u2_n000596 : X_LUT4
    generic map(
      INIT => X"0500"
    )
    port map (
      ADR0 => key2_IBUF_0,
      ADR1 => VCC,
      ADR2 => key0_IBUF_0,
      ADR3 => CHOICE699,
      O => CHOICE700
    );
  CHOICE699_XUSED : X_BUF
    port map (
      I => CHOICE699_pack_1,
      O => CHOICE699
    );
  CHOICE699_YUSED : X_BUF
    port map (
      I => CHOICE700,
      O => CHOICE700_0
    );
  u3_COUNT_3_n00001 : X_LUT4
    generic map(
      INIT => X"FF50"
    )
    port map (
      ADR0 => u2_Qn_3_Q,
      ADR1 => VCC,
      ADR2 => u2_kload,
      ADR3 => u1_Counter_Reset,
      O => u3_COUNT_0_3_n0000
    );
  u3_COUNT_1_n00001 : X_LUT4
    generic map(
      INIT => X"BBAA"
    )
    port map (
      ADR0 => u1_Counter_Reset,
      ADR1 => u2_Qn_1_Q,
      ADR2 => VCC,
      ADR3 => u2_kload,
      O => u3_COUNT_0_1_n0000
    );
  u3_COUNT_0_3_n0000_XUSED : X_BUF
    port map (
      I => u3_COUNT_0_3_n0000,
      O => u3_COUNT_0_3_n0000_0
    );
  u3_COUNT_0_3_n0000_YUSED : X_BUF
    port map (
      I => u3_COUNT_0_1_n0000,
      O => u3_COUNT_0_1_n0000_0
    );
  u4_n00241 : X_LUT4
    generic map(
      INIT => X"0F0A"
    )
    port map (
      ADR0 => u4_n0012_0,
      ADR1 => VCC,
      ADR2 => u4_n0005_0,
      ADR3 => u4_n0011_0,
      O => u4_n0024
    );
  u4_n00061 : X_LUT4
    generic map(
      INIT => X"5500"
    )
    port map (
      ADR0 => u4_n0005_0,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => u4_n0011_0,
      O => u4_n0006
    );
  u4_n0024_XUSED : X_BUF
    port map (
      I => u4_n0024,
      O => u4_n0024_0
    );
  u4_n0024_YUSED : X_BUF
    port map (
      I => u4_n0006,
      O => u4_n0006_0
    );
  u4_n00221 : X_LUT4
    generic map(
      INIT => X"0002"
    )
    port map (
      ADR0 => u4_n0021,
      ADR1 => u4_n0012_0,
      ADR2 => u4_n0011_0,
      ADR3 => u4_n0005_0,
      O => u4_n0022
    );
  u4_n0022_YUSED : X_BUF
    port map (
      I => u4_n0022,
      O => u4_n0022_0
    );
  u6_n0007_3_1 : X_LUT4
    generic map(
      INIT => X"FF7F"
    )
    port map (
      ADR0 => u6_countb_4_Q,
      ADR1 => u6_countb_3_Q,
      ADR2 => u6_countb_2_Q,
      ADR3 => u6_countb_1_Q,
      O => u6_N29_pack_1
    );
  u6_n0007_0_2 : X_LUT4
    generic map(
      INIT => X"0011"
    )
    port map (
      ADR0 => u6_countb_0_Q,
      ADR1 => u6_countc_0_Q,
      ADR2 => VCC,
      ADR3 => u6_N29,
      O => u6_n0007_0_Q
    );
  u6_countc_0_XUSED : X_BUF
    port map (
      I => u6_N29_pack_1,
      O => u6_N29
    );
  u6_countc_0 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => u6_n0007_0_Q,
      CE => u6_n0024_0,
      CLK => Clk_BUFGP,
      SET => GND,
      RST => u6_countc_0_FFY_RST,
      O => u6_countc_0_Q
    );
  u6_countc_0_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => u6_countc_0_FFY_RST
    );
  u3_COUNT_2_n00011 : X_LUT4
    generic map(
      INIT => X"C0C0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => u2_kload,
      ADR2 => u2_Qn_2_Q,
      ADR3 => VCC,
      O => u3_COUNT_0_2_n0001
    );
  u3_COUNT_3_n00011 : X_LUT4
    generic map(
      INIT => X"CC00"
    )
    port map (
      ADR0 => VCC,
      ADR1 => u2_kload,
      ADR2 => VCC,
      ADR3 => u2_Qn_3_Q,
      O => u3_COUNT_0_3_n0001
    );
  u6_n0012_SW0 : X_LUT4
    generic map(
      INIT => X"F000"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => u6_countc_4_Q,
      ADR3 => u6_countc_3_Q,
      O => N210
    );
  N210_YUSED : X_BUF
    port map (
      I => N210,
      O => N210_0
    );
  u6_n00241 : X_LUT4
    generic map(
      INIT => X"0F0C"
    )
    port map (
      ADR0 => VCC,
      ADR1 => u6_n0012,
      ADR2 => u6_n0005_0,
      ADR3 => u6_n0011_0,
      O => u6_n0024
    );
  u6_n00061 : X_LUT4
    generic map(
      INIT => X"0F00"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => u6_n0005_0,
      ADR3 => u6_n0011_0,
      O => u6_n0006
    );
  u6_n0024_XUSED : X_BUF
    port map (
      I => u6_n0024,
      O => u6_n0024_0
    );
  u6_n0024_YUSED : X_BUF
    port map (
      I => u6_n0006,
      O => u6_n0006_0
    );
  u6_n00221 : X_LUT4
    generic map(
      INIT => X"0010"
    )
    port map (
      ADR0 => u6_n0005_0,
      ADR1 => u6_n0012,
      ADR2 => u6_n0021_0,
      ADR3 => u6_n0011_0,
      O => u6_n0022
    );
  u6_n0022_YUSED : X_BUF
    port map (
      I => u6_n0022,