microoven_timesim.vhd

微波爐．．．．．．．．．．．．．．．．．．．．．．．．．．

--------------------------------------------------------------------------------
-- Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.
--------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor: Xilinx
-- \   \   \/     Version: H.42
--  \   \         Application: netgen
--  /   /         Filename: microoven_timesim.vhd
-- /___/   /\     Timestamp: Wed Mar 11 10:28:28 2009
-- \   \  /  \ 
--  \___\/\___\
--             
-- Command	: -intstyle ise -s 6 -pcf microoven.pcf -rpw 100 -tpw 0 -ar Structure -xon true -w -ofmt vhdl -sim microoven.ncd microoven_timesim.vhd 
-- Device	: 2s50etq144-6 (PRODUCTION 1.18 2005-01-22)
-- Input file	: microoven.ncd
-- Output file	: microoven_timesim.vhd
-- # of Entities	: 1
-- Design Name	: microoven
-- Xilinx	: c:/xilinx
--             
-- Purpose:    
--     This VHDL netlist is a verification model and uses simulation 
--     primitives which may not represent the true implementation of the 
--     device, however the netlist is functionally correct and should not 
--     be modified. This file cannot be synthesized and should only be used 
--     with supported simulation tools.
--             
-- Reference:  
--     Development System Reference Guide, Chapter 23
--     Synthesis and Verification Design Guide, Chapter 6
--             
--------------------------------------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library SIMPRIM;
use SIMPRIM.VCOMPONENTS.ALL;
use SIMPRIM.VPACKAGE.ALL;

entity microoven is
  port (
    Clk : in STD_LOGIC := 'X'; 
    key0 : in STD_LOGIC := 'X'; 
    key1 : in STD_LOGIC := 'X'; 
    key2 : in STD_LOGIC := 'X'; 
    key3 : in STD_LOGIC := 'X'; 
    key4 : in STD_LOGIC := 'X'; 
    key5 : in STD_LOGIC := 'X'; 
    key6 : in STD_LOGIC := 'X'; 
    key7 : in STD_LOGIC := 'X'; 
    key8 : in STD_LOGIC := 'X'; 
    key9 : in STD_LOGIC := 'X'; 
    Start : in STD_LOGIC := 'X'; 
    Clear : in STD_LOGIC := 'X'; 
    Door : in STD_LOGIC := 'X'; 
    Set : in STD_LOGIC := 'X'; 
    a : out STD_LOGIC; 
    b : out STD_LOGIC; 
    c : out STD_LOGIC; 
    d : out STD_LOGIC; 
    e : out STD_LOGIC; 
    f : out STD_LOGIC; 
    g : out STD_LOGIC; 
    L_LED : out STD_LOGIC; 
    H_LED : out STD_LOGIC; 
    M_LED : out STD_LOGIC 
  );
end microoven;

architecture Structure of microoven is
  signal Set_IBUF_0 : STD_LOGIC; 
  signal u4_B : STD_LOGIC; 
  signal u2_N16_0 : STD_LOGIC; 
  signal u2_N14 : STD_LOGIC; 
  signal key8_IBUF_0 : STD_LOGIC; 
  signal key9_IBUF_0 : STD_LOGIC; 
  signal key3_IBUF_0 : STD_LOGIC; 
  signal key2_IBUF_0 : STD_LOGIC; 
  signal N6_0 : STD_LOGIC; 
  signal u2_N15 : STD_LOGIC; 
  signal u2_Qn_3_Q : STD_LOGIC; 
  signal u2_Qn_2_Q : STD_LOGIC; 
  signal u3_n0005_0 : STD_LOGIC; 
  signal u2_Qn_0_Q : STD_LOGIC; 
  signal u2_kload : STD_LOGIC; 
  signal u3_COUNT_0_Q : STD_LOGIC; 
  signal u3_COUNT_0_0_n0000_0 : STD_LOGIC; 
  signal u2_Qn_1_Q : STD_LOGIC; 
  signal u3_COUNT_1_Q : STD_LOGIC; 
  signal u3_COUNT_0_1_n0000_0 : STD_LOGIC; 
  signal u6_B : STD_LOGIC; 
  signal u1_temp_LED_1_Q : STD_LOGIC; 
  signal key7_IBUF_0 : STD_LOGIC; 
  signal u1_temp_LED_0_Q : STD_LOGIC; 
  signal Clear_IBUF_0 : STD_LOGIC; 
  signal key6_IBUF_0 : STD_LOGIC; 
  signal key5_IBUF_0 : STD_LOGIC; 
  signal key4_IBUF_0 : STD_LOGIC; 
  signal u1_temp_LED_2_Q : STD_LOGIC; 
  signal u4_n0025_0 : STD_LOGIC; 
  signal Clk_BUFGP : STD_LOGIC; 
  signal u4_countc_2_Q : STD_LOGIC; 
  signal u4_countc_4_Q : STD_LOGIC; 
  signal u4_countc_5_Q : STD_LOGIC; 
  signal u4_countc_3_Q : STD_LOGIC; 
  signal u4_countd_0_Q : STD_LOGIC; 
  signal u4_countc_0_Q : STD_LOGIC; 
  signal u4_N19 : STD_LOGIC; 
  signal u4_countc_1_Q : STD_LOGIC; 
  signal u4_countd_4_Q : STD_LOGIC; 
  signal u4_countd_5_Q : STD_LOGIC; 
  signal u4_countd_3_Q : STD_LOGIC; 
  signal N216_0 : STD_LOGIC; 
  signal key0_IBUF_0 : STD_LOGIC; 
  signal N4_0 : STD_LOGIC; 
  signal CHOICE688_0 : STD_LOGIC; 
  signal CHOICE699 : STD_LOGIC; 
  signal CHOICE700_0 : STD_LOGIC; 
  signal u1_Counter_Reset : STD_LOGIC; 
  signal u3_COUNT_0_3_n0000_0 : STD_LOGIC; 
  signal u4_n0011_0 : STD_LOGIC; 
  signal u4_n0005_0 : STD_LOGIC; 
  signal u4_n0012_0 : STD_LOGIC; 
  signal u4_n0024_0 : STD_LOGIC; 
  signal u4_n0006_0 : STD_LOGIC; 
  signal u4_n0021 : STD_LOGIC; 
  signal u4_n0022_0 : STD_LOGIC; 
  signal u6_n0024_0 : STD_LOGIC; 
  signal u6_countb_2_Q : STD_LOGIC; 
  signal u6_countb_3_Q : STD_LOGIC; 
  signal u6_countb_4_Q : STD_LOGIC; 
  signal u6_countb_1_Q : STD_LOGIC; 
  signal u6_countc_0_Q : STD_LOGIC; 
  signal u6_countb_0_Q : STD_LOGIC; 
  signal u6_N29 : STD_LOGIC; 
  signal u6_countc_3_Q : STD_LOGIC; 
  signal u6_countc_4_Q : STD_LOGIC; 
  signal N210_0 : STD_LOGIC; 
  signal u6_n0011_0 : STD_LOGIC; 
  signal u6_n0005_0 : STD_LOGIC; 
  signal u6_n0012 : STD_LOGIC; 
  signal u6_n0006_0 : STD_LOGIC; 
  signal u6_n0021_0 : STD_LOGIC; 
  signal u6_n0022_0 : STD_LOGIC; 
  signal u1_EN_N1 : STD_LOGIC; 
  signal u1_EN : STD_LOGIC; 
  signal Start_IBUF_0 : STD_LOGIC; 
  signal u3_COUNT_3_Q : STD_LOGIC; 
  signal u3_COUNT_2_Q : STD_LOGIC; 
  signal u6_n0025_0 : STD_LOGIC; 
  signal u6_countc_2_Q : STD_LOGIC; 
  signal u6_countc_1_Q : STD_LOGIC; 
  signal u6_countd_0_Q : STD_LOGIC; 
  signal u6_N17 : STD_LOGIC; 
  signal N101_0 : STD_LOGIC; 
  signal CHOICE703 : STD_LOGIC; 
  signal u4_countb_2_Q : STD_LOGIC; 
  signal u4_countb_4_Q : STD_LOGIC; 
  signal u4_countb_5_Q : STD_LOGIC; 
  signal u4_countb_3_Q : STD_LOGIC; 
  signal u4_countb_0_Q : STD_LOGIC; 
  signal u4_N33 : STD_LOGIC; 
  signal u4_countb_1_Q : STD_LOGIC; 
  signal u3_COUNT_0_2_n0000_0 : STD_LOGIC; 
  signal CHOICE670_0 : STD_LOGIC; 
  signal key1_IBUF_0 : STD_LOGIC; 
  signal GLOBAL_LOGIC1 : STD_LOGIC; 
  signal GLOBAL_LOGIC0 : STD_LOGIC; 
  signal u4_countd_1_Q : STD_LOGIC; 
  signal u4_n0010_1_0 : STD_LOGIC; 
  signal u4_countd_2_Q : STD_LOGIC; 
  signal u4_n0010_2_0 : STD_LOGIC; 
  signal u4_n0010_3_0 : STD_LOGIC; 
  signal u4_n0010_4_0 : STD_LOGIC; 
  signal u4_n0010_5_0 : STD_LOGIC; 
  signal u4_n0009_1_0 : STD_LOGIC; 
  signal u4_n0009_2_0 : STD_LOGIC; 
  signal u4_n0009_3_0 : STD_LOGIC; 
  signal u4_n0009_4_0 : STD_LOGIC; 
  signal u4_n0009_5_0 : STD_LOGIC; 
  signal u6_countd_1_Q : STD_LOGIC; 
  signal u6_n0010_1_0 : STD_LOGIC; 
  signal u6_countd_2_Q : STD_LOGIC; 
  signal u6_countd_3_Q : STD_LOGIC; 
  signal u6_n0010_2_0 : STD_LOGIC; 
  signal u6_n0010_3_0 : STD_LOGIC; 
  signal u6_countd_4_Q : STD_LOGIC; 
  signal u6_n0010_4_0 : STD_LOGIC; 
  signal u6_counta_0_Q : STD_LOGIC; 
  signal u6_counta_1_Q : STD_LOGIC; 
  signal u6_counta_2_Q : STD_LOGIC; 
  signal u6_counta_3_Q : STD_LOGIC; 
  signal u6_counta_4_Q : STD_LOGIC; 
  signal u6_n0009_1_0 : STD_LOGIC; 
  signal u6_n0009_2_0 : STD_LOGIC; 
  signal u6_n0009_3_0 : STD_LOGIC; 
  signal u6_n0009_4_0 : STD_LOGIC; 
  signal u4_counta_0_Q : STD_LOGIC; 
  signal u4_counta_1_Q : STD_LOGIC; 
  signal u4_counta_2_Q : STD_LOGIC; 
  signal u4_counta_3_Q : STD_LOGIC; 
  signal u4_counta_4_Q : STD_LOGIC; 
  signal u4_counta_5_Q : STD_LOGIC; 
  signal u3_COUNT_n0001_2_SW0_O : STD_LOGIC; 
  signal u3_COUNT_n0001_3_SW0_O : STD_LOGIC; 
  signal u6_n0011_SW0_O : STD_LOGIC; 
  signal u6_n0005_SW0_O : STD_LOGIC; 
  signal u6_n0021_SW0_O : STD_LOGIC; 
  signal u3_n00051_O : STD_LOGIC; 
  signal u4_n0011_SW0_O : STD_LOGIC; 
  signal u4_n0012_SW0_O : STD_LOGIC; 
  signal u4_n0005_SW0_O : STD_LOGIC; 
  signal GSR : STD_LOGIC; 
  signal GTS : STD_LOGIC; 
  signal u2_n0002_3_Q : STD_LOGIC; 
  signal u2_n0002_2_Q : STD_LOGIC; 
  signal u3_COUNT_0_0_n0001_pack_1 : STD_LOGIC; 
  signal u3_COUNT_n0001_0_Q : STD_LOGIC; 
  signal u3_COUNT_0_FFY_SET : STD_LOGIC; 
  signal u3_COUNT_0_FFY_RST : STD_LOGIC; 
  signal u3_COUNT_0_1_n0001_pack_1 : STD_LOGIC; 
  signal u3_COUNT_n0001_1_Q : STD_LOGIC; 
  signal u3_COUNT_1_FFY_SET : STD_LOGIC; 
  signal u3_COUNT_1_FFY_RST : STD_LOGIC; 
  signal u1_n0003_1_Q : STD_LOGIC; 
  signal u1_temp_LED_1_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal u1_n0003_0_Q : STD_LOGIC; 
  signal u1_temp_LED_1_CEMUXNOT : STD_LOGIC; 
  signal N6 : STD_LOGIC; 
  signal u1_temp_LED_2_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal u1_n0003_2_Q : STD_LOGIC; 
  signal u1_temp_LED_2_CEMUXNOT : STD_LOGIC; 
  signal u4_N19_pack_1 : STD_LOGIC; 
  signal u4_n0008_0_Q : STD_LOGIC; 
  signal u4_countd_0_FFY_RST : STD_LOGIC; 
  signal N216 : STD_LOGIC; 
  signal N4 : STD_LOGIC; 
  signal CHOICE688 : STD_LOGIC; 
  signal CHOICE699_pack_1 : STD_LOGIC; 
  signal CHOICE700 : STD_LOGIC; 
  signal u3_COUNT_0_3_n0000 : STD_LOGIC; 
  signal u3_COUNT_0_1_n0000 : STD_LOGIC; 
  signal u4_n0024 : STD_LOGIC; 
  signal u4_n0006 : STD_LOGIC; 
  signal u4_n0022 : STD_LOGIC; 
  signal u6_N29_pack_1 : STD_LOGIC; 
  signal u6_n0007_0_Q : STD_LOGIC; 
  signal u6_countc_0_FFY_RST : STD_LOGIC; 
  signal u3_COUNT_0_2_n0001 : STD_LOGIC; 
  signal u3_COUNT_0_3_n0001 : STD_LOGIC; 
  signal N210 : STD_LOGIC; 
  signal u6_n0024 : STD_LOGIC; 
  signal u6_n0006 : STD_LOGIC; 
  signal u6_n0022 : STD_LOGIC; 
  signal u1_n0002 : STD_LOGIC; 
  signal u1_EN_N1_pack_1 : STD_LOGIC; 
  signal u1_EN_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal f_OBUF : STD_LOGIC; 
  signal a_OBUF : STD_LOGIC; 
  signal u4_counta_4_LOGIC_ZERO : STD_LOGIC; 
  signal u4_counta_4_FROM : STD_LOGIC; 
  signal u4_counta_n0000_4_Q : STD_LOGIC; 
  signal u4_counta_5_rt : STD_LOGIC; 
  signal u4_clkdiv2_counta_n0000_4_cyo : STD_LOGIC; 
  signal u4_counta_4_CYINIT : STD_LOGIC; 
  signal u4_counta_n0000_5_Q : STD_LOGIC; 
  signal u3_COUNT_n0001_2_SW0_O_pack_1 : STD_LOGIC; 
  signal u3_COUNT_n0001_2_O : STD_LOGIC; 
  signal u3_COUNT_2_FFY_SET : STD_LOGIC; 
  signal u3_COUNT_2_FFY_RST : STD_LOGIC; 
  signal u3_COUNT_n0001_3_SW0_O_pack_1 : STD_LOGIC; 
  signal u3_COUNT_n0001_3_O : STD_LOGIC; 
  signal u3_COUNT_3_FFY_SET : STD_LOGIC; 
  signal u3_COUNT_3_FFY_RST : STD_LOGIC; 
  signal u4_n0021_pack_1 : STD_LOGIC; 
  signal u4_n0025 : STD_LOGIC; 
  signal u6_n0011_SW0_O_pack_1 : STD_LOGIC; 
  signal u6_n0011 : STD_LOGIC; 
  signal u6_n0005_SW0_O_pack_1 : STD_LOGIC; 
  signal u6_n0005 : STD_LOGIC; 
  signal u6_n0021_SW0_O_pack_1 : STD_LOGIC; 
  signal u6_n0021 : STD_LOGIC; 
  signal u6_n0012_pack_1 : STD_LOGIC; 
  signal u6_n0025 : STD_LOGIC; 
  signal u4_n0007_1_2_O : STD_LOGIC; 
  signal u4_countc_1_FFY_RST : STD_LOGIC; 
  signal u4_n0007_3_2_O : STD_LOGIC; 
  signal u4_n0007_2_2_O : STD_LOGIC; 
  signal u4_n0007_5_2_O : STD_LOGIC; 
  signal u4_n0007_4_2_O : STD_LOGIC; 
  signal u4_n0008_1_2_O : STD_LOGIC; 
  signal u4_countd_1_FFY_RST : STD_LOGIC; 
  signal u4_n0008_3_2_O : STD_LOGIC; 
  signal u4_n0008_2_2_O : STD_LOGIC; 
  signal u4_n0008_5_2_O : STD_LOGIC; 
  signal u4_n0008_4_2_O : STD_LOGIC; 
  signal u3_n00051_O_pack_1 : STD_LOGIC; 
  signal u3_n0005 : STD_LOGIC; 
  signal u6_n0007_4_2_O : STD_LOGIC; 
  signal u6_n0007_1_2_O : STD_LOGIC; 
  signal u6_N6 : STD_LOGIC; 
  signal u6_n0010_1_CYMUXG : STD_LOGIC; 
  signal u6_n0010_1_Q : STD_LOGIC; 
  signal u6_n0010_1_GROM : STD_LOGIC; 
  signal u6_clkdiv3_n0010_0_cyo : STD_LOGIC; 
  signal u6_n0010_1_LOGIC_ZERO : STD_LOGIC; 
  signal u6_n0010_2_FROM : STD_LOGIC; 
  signal u6_n0010_2_Q : STD_LOGIC; 
  signal u6_n0010_2_CYMUXG : STD_LOGIC; 
  signal u6_n0010_2_LOGIC_ZERO : STD_LOGIC; 
  signal u6_n0010_3_Q : STD_LOGIC; 
  signal u6_n0010_2_GROM : STD_LOGIC; 
  signal u6_clkdiv3_n0010_2_cyo : STD_LOGIC; 
  signal u6_n0010_2_CYINIT : STD_LOGIC; 
  signal u6_countd_4_rt : STD_LOGIC; 
  signal u6_n0010_4_Q : STD_LOGIC; 
  signal u6_n0010_4_CYINIT : STD_LOGIC; 
  signal u6_N9 : STD_LOGIC; 
  signal u6_counta_0_CYMUXG : STD_LOGIC; 
  signal u6_counta_0_GROM : STD_LOGIC; 
  signal u6_clkdiv3_counta_n0000_0_cyo : STD_LOGIC; 
  signal u6_counta_0_LOGIC_ZERO : STD_LOGIC; 
  signal u6_counta_n0000_1_Q : STD_LOGIC; 
  signal u6_counta_2_FROM : STD_LOGIC; 
  signal u6_counta_n0000_2_Q : STD_LOGIC; 
  signal u6_counta_2_CYMUXG : STD_LOGIC; 
  signal u6_counta_2_LOGIC_ZERO : STD_LOGIC; 
  signal u6_counta_2_GROM : STD_LOGIC; 
  signal u6_clkdiv3_counta_n0000_2_cyo : STD_LOGIC; 
  signal u6_counta_2_CYINIT : STD_LOGIC; 
  signal u6_counta_n0000_3_Q : STD_LOGIC; 
  signal u6_counta_4_rt : STD_LOGIC; 
  signal u6_counta_n0000_4_Q : STD_LOGIC; 
  signal u6_counta_4_CYINIT : STD_LOGIC; 
  signal u6_N7 : STD_LOGIC; 
  signal u6_n0009_1_CYMUXG : STD_LOGIC; 
  signal u6_n0009_1_Q : STD_LOGIC; 
  signal u6_n0009_1_GROM : STD_LOGIC; 
  signal u6_clkdiv3_n0009_0_cyo : STD_LOGIC; 
  signal u6_n0009_1_LOGIC_ZERO : STD_LOGIC; 
  signal u6_n0009_2_FROM : STD_LOGIC; 
  signal u6_n0009_2_Q : STD_LOGIC; 
  signal u6_n0009_2_CYMUXG : STD_LOGIC; 
  signal u6_n0009_2_LOGIC_ZERO : STD_LOGIC; 
  signal u6_n0009_3_Q : STD_LOGIC; 
  signal u6_n0009_2_GROM : STD_LOGIC; 
  signal u6_clkdiv3_n0009_2_cyo : STD_LOGIC; 
  signal u6_n0009_2_CYINIT : STD_LOGIC; 
  signal u6_countc_4_rt : STD_LOGIC; 
  signal u6_n0009_4_Q : STD_LOGIC; 
  signal u6_n0009_4_CYINIT : STD_LOGIC; 
  signal u4_N9 : STD_LOGIC; 
  signal u4_counta_0_CYMUXG : STD_LOGIC; 
  signal u4_counta_0_GROM : STD_LOGIC; 
  signal u4_clkdiv2_counta_n0000_0_cyo : STD_LOGIC; 
  signal u4_counta_0_LOGIC_ZERO : STD_LOGIC; 
  signal u4_counta_n0000_1_Q : STD_LOGIC; 
  signal u4_counta_2_FROM : STD_LOGIC; 
  signal u4_counta_n0000_2_Q : STD_LOGIC; 
  signal u4_counta_2_CYMUXG : STD_LOGIC; 
  signal u4_counta_2_LOGIC_ZERO : STD_LOGIC; 
  signal u4_counta_2_GROM : STD_LOGIC; 
  signal u4_clkdiv2_counta_n0000_2_cyo : STD_LOGIC; 
  signal u4_counta_2_CYINIT : STD_LOGIC; 
  signal u4_counta_n0000_3_Q : STD_LOGIC; 
  signal u4_n0010_4_LOGIC_ZERO : STD_LOGIC; 
  signal u4_n0010_4_FROM : STD_LOGIC; 
  signal u4_n0010_4_Q : STD_LOGIC; 
  signal u4_n0010_5_Q : STD_LOGIC; 
  signal u4_countd_5_rt : STD_LOGIC; 
  signal u4_clkdiv2_n0010_4_cyo : STD_LOGIC; 
  signal u4_n0010_4_CYINIT : STD_LOGIC; 
  signal u6_N8 : STD_LOGIC; 
  signal u6_countb_0_CYMUXG : STD_LOGIC; 
  signal u6_countb_0_GROM : STD_LOGIC; 
  signal u6_clkdiv3_countb_n0000_0_cyo : STD_LOGIC; 
  signal u6_countb_0_LOGIC_ZERO : STD_LOGIC; 
  signal u6_countb_n0000_1_Q : STD_LOGIC; 
  signal u6_countb_2_FROM : STD_LOGIC; 
  signal u6_countb_n0000_2_Q : STD_LOGIC; 
  signal u6_countb_2_CYMUXG : STD_LOGIC; 
  signal u6_countb_2_LOGIC_ZERO : STD_LOGIC; 
  signal u6_countb_2_GROM : STD_LOGIC; 
  signal u6_clkdiv3_countb_n0000_2_cyo : STD_LOGIC; 
  signal u6_countb_2_CYINIT : STD_LOGIC; 
  signal u6_countb_n0000_3_Q : STD_LOGIC; 
  signal u6_countb_4_rt : STD_LOGIC; 
  signal u6_countb_n0000_4_Q : STD_LOGIC; 
  signal u6_countb_4_CYINIT : STD_LOGIC; 
  signal u4_N7 : STD_LOGIC; 
  signal u4_n0009_1_CYMUXG : STD_LOGIC; 
  signal u4_n0009_1_Q : STD_LOGIC; 
  signal u4_n0009_1_GROM : STD_LOGIC; 
  signal u4_clkdiv2_n0009_0_cyo : STD_LOGIC; 
  signal u4_n0009_1_LOGIC_ZERO : STD_LOGIC; 
  signal u4_n0009_2_FROM : STD_LOGIC; 
  signal u4_n0009_2_Q : STD_LOGIC; 
  signal u4_n0009_2_CYMUXG : STD_LOGIC; 
  signal u4_n0009_2_LOGIC_ZERO : STD_LOGIC; 
  signal u4_n0009_3_Q : STD_LOGIC; 
  signal u4_n0009_2_GROM : STD_LOGIC; 
  signal u4_clkdiv2_n0009_2_cyo : STD_LOGIC; 
  signal u4_n0009_2_CYINIT : STD_LOGIC; 
  signal u4_n0009_4_LOGIC_ZERO : STD_LOGIC; 
  signal u4_n0009_4_FROM : STD_LOGIC; 
  signal u4_n0009_4_Q : STD_LOGIC; 
  signal u4_n0009_5_Q : STD_LOGIC; 
  signal u4_countc_5_rt : STD_LOGIC; 
  signal u4_clkdiv2_n0009_4_cyo : STD_LOGIC; 
  signal u4_n0009_4_CYINIT : STD_LOGIC; 
  signal u4_N8 : STD_LOGIC; 
  signal u4_countb_0_CYMUXG : STD_LOGIC; 
  signal u4_countb_0_GROM : STD_LOGIC; 
  signal u4_clkdiv2_countb_n0000_0_cyo : STD_LOGIC; 
  signal u4_countb_0_LOGIC_ZERO : STD_LOGIC; 
  signal u4_countb_n0000_1_Q : STD_LOGIC; 
  signal u4_countb_2_FROM : STD_LOGIC; 
  signal u4_countb_n0000_2_Q : STD_LOGIC; 
  signal u4_countb_2_CYMUXG : STD_LOGIC; 
  signal u4_countb_2_LOGIC_ZERO : STD_LOGIC; 
  signal u4_countb_2_GROM : STD_LOGIC; 
  signal u4_clkdiv2_countb_n0000_2_cyo : STD_LOGIC; 
  signal u4_countb_2_CYINIT : STD_LOGIC; 
  signal u4_countb_n0000_3_Q : STD_LOGIC; 
  signal u4_countb_4_LOGIC_ZERO : STD_LOGIC; 
  signal u4_countb_4_FROM : STD_LOGIC; 
  signal u4_countb_n0000_4_Q : STD_LOGIC; 
  signal u4_countb_5_rt : STD_LOGIC; 
  signal u4_clkdiv2_countb_n0000_4_cyo : STD_LOGIC; 
  signal u4_countb_4_CYINIT : STD_LOGIC; 
  signal u4_countb_n0000_5_Q : STD_LOGIC; 
  signal key5_IBUF : STD_LOGIC; 
  signal key6_IBUF : STD_LOGIC; 
  signal key7_IBUF : STD_LOGIC; 
  signal key8_IBUF : STD_LOGIC; 
  signal key9_IBUF : STD_LOGIC; 
  signal Set_IBUF : STD_LOGIC; 
  signal Start_IBUF : STD_LOGIC; 
  signal L_LED_ENABLE : STD_LOGIC; 
  signal L_LED_OUTMUX : STD_LOGIC; 
  signal M_LED_ENABLE : STD_LOGIC; 
  signal M_LED_OUTMUX : STD_LOGIC; 
  signal a_ENABLE : STD_LOGIC; 
  signal a_OUTMUX : STD_LOGIC; 
  signal b_ENABLE : STD_LOGIC; 
  signal b_OUTMUX : STD_LOGIC; 
  signal H_LED_ENABLE : STD_LOGIC; 
  signal H_LED_OUTMUX : STD_LOGIC; 
  signal c_ENABLE : STD_LOGIC; 
  signal c_OUTMUX : STD_LOGIC; 
  signal d_ENABLE : STD_LOGIC; 
  signal d_OUTMUX : STD_LOGIC; 
  signal N232 : STD_LOGIC; 
  signal N231 : STD_LOGIC; 
  signal CHOICE670 : STD_LOGIC; 
  signal u4_N6 : STD_LOGIC; 
  signal u4_n0010_1_CYMUXG : STD_LOGIC; 
  signal u4_n0010_1_Q : STD_LOGIC; 
  signal u4_n0010_1_GROM : STD_LOGIC; 
  signal u4_clkdiv2_n0010_0_cyo : STD_LOGIC; 
  signal u4_n0010_1_LOGIC_ZERO : STD_LOGIC; 
  signal u4_n0010_2_FROM : STD_LOGIC; 
  signal u4_n0010_2_Q : STD_LOGIC; 
  signal u4_n0010_2_CYMUXG : STD_LOGIC; 
  signal u4_n0010_2_LOGIC_ZERO : STD_LOGIC; 
  signal u4_n0010_3_Q : STD_LOGIC; 
  signal u4_n0010_2_GROM : STD_LOGIC; 
  signal u4_clkdiv2_n0010_2_cyo : STD_LOGIC; 
  signal u4_n0010_2_CYINIT : STD_LOGIC; 
  signal u6_N17_pack_1 : STD_LOGIC; 
  signal u6_n0008_0_Q : STD_LOGIC; 
  signal u6_countd_0_FFY_RST : STD_LOGIC; 
  signal u1_Counter_Reset_LOGIC_ONE : STD_LOGIC; 
  signal e_OBUF : STD_LOGIC; 
  signal b_OBUF : STD_LOGIC; 
  signal d_OBUF : STD_LOGIC; 
  signal c_OBUF : STD_LOGIC; 
  signal g_OBUF : STD_LOGIC; 
  signal CHOICE703_pack_1 : STD_LOGIC; 
  signal N195 : STD_LOGIC; 
  signal u2_kload_FFY_RST : STD_LOGIC; 
  signal u4_N33_pack_1 : STD_LOGIC; 
  signal u4_n0007_0_Q : STD_LOGIC; 
  signal u4_countc_0_FFY_RST : STD_LOGIC; 
  signal u3_COUNT_0_2_n0000 : STD_LOGIC; 
  signal u3_COUNT_0_0_n0000 : STD_LOGIC; 
  signal u4_B_BYMUXNOT : STD_LOGIC; 
  signal u4_B_FFY_RST : STD_LOGIC; 
  signal u2_N14_pack_1 : STD_LOGIC; 
  signal N101 : STD_LOGIC; 
  signal u2_Qn_0_FFY_RST : STD_LOGIC; 
  signal u2_N15_pack_1 : STD_LOGIC; 
  signal u2_n0002_1_Q : STD_LOGIC; 
  signal u2_Qn_1_FFY_RST : STD_LOGIC; 
  signal u2_N16 : STD_LOGIC; 
  signal u6_B_BYMUXNOT : STD_LOGIC; 
  signal u6_B_FFY_RST : STD_LOGIC; 
  signal e_ENABLE : STD_LOGIC; 
  signal e_OUTMUX : STD_LOGIC; 
  signal f_ENABLE : STD_LOGIC; 
  signal f_OUTMUX : STD_LOGIC; 
  signal g_ENABLE : STD_LOGIC; 
  signal g_OUTMUX : STD_LOGIC; 
  signal Door_IBUF : STD_LOGIC; 
  signal Clear_IBUF : STD_LOGIC; 
  signal key0_IBUF : STD_LOGIC; 
  signal key1_IBUF : STD_LOGIC; 
  signal key2_IBUF : STD_LOGIC; 
  signal key3_IBUF : STD_LOGIC; 
  signal key4_IBUF : STD_LOGIC; 
  signal u6_n0007_3_2_O : STD_LOGIC; 
  signal u6_n0007_2_2_O : STD_LOGIC; 
  signal u6_n0008_4_2_O : STD_LOGIC; 
  signal u6_n0008_1_2_O : STD_LOGIC; 
  signal u6_countd_4_FFX_RST : STD_LOGIC; 
  signal u6_n0008_3_2_O : STD_LOGIC; 
  signal u6_n0008_2_2_O : STD_LOGIC; 
  signal u6_countd_3_FFX_RST : STD_LOGIC; 
  signal u4_n0011_SW0_O_pack_1 : STD_LOGIC; 
  signal u4_n0011 : STD_LOGIC; 
  signal u4_n0012_SW0_O_pack_1 : STD_LOGIC; 
  signal u4_n0012 : STD_LOGIC; 
  signal u4_n0005_SW0_O_pack_1 : STD_LOGIC; 
  signal u4_n0005 : STD_LOGIC; 
  signal u4_countc_3_FFY_RST : STD_LOGIC; 
  signal u4_countc_5_FFY_RST : STD_LOGIC; 
  signal u4_countd_3_FFY_RST : STD_LOGIC; 
  signal u4_countd_5_FFY_RST : STD_LOGIC; 
  signal u6_countc_4_FFY_RST : STD_LOGIC; 
  signal u6_countc_3_FFY_RST : STD_LOGIC; 
  signal u6_countd_4_FFY_RST : STD_LOGIC; 
  signal u6_countd_3_FFY_RST : STD_LOGIC; 
  signal u2_Qn_3_FFX_RST : STD_LOGIC; 
  signal u1_EN_FFX_RST : STD_LOGIC; 
  signal u2_Qn_3_FFY_RST : STD_LOGIC;