picunit.syr

微波爐．．．．．．．．．．．．．．．．．．．．．．．．．．

Release 7.1.04i - xst H.42
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to __projnav
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--> Parameter xsthdpdir set to ./xst
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--> Reading design: picunit.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
  5) Advanced HDL Synthesis
     5.1) HDL Synthesis Report
  6) Low Level Synthesis
  7) Final Report
     7.1) Device utilization summary
     7.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : "picunit.prj"
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO

---- Target Parameters
Output File Name                   : "picunit"
Output Format                      : NGC
Target Device                      : xc2s50e-6-tq144

---- Source Options
Top Module Name                    : picunit
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
ROM Style                          : Auto
Mux Extraction                     : YES
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
Resource Sharing                   : YES
Multiplier Style                   : lut
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 100
Add Generic Clock Buffer(BUFG)     : 4
Register Duplication               : YES
Equivalent register Removal        : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : NO
Global Optimization                : AllClockNets
RTL Output                         : Yes
Write Timing Constraints           : NO
Hierarchy Separator                : /
Bus Delimiter                      : <>
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
Slice Utilization Ratio Delta      : 5

---- Other Options
lso                                : picunit.lso
Read Cores                         : YES
cross_clock_analysis               : NO
verilog2001                        : YES
safe_implementation                : No
Optimize Instantiated Primitives   : NO
tristate2logic                     : Yes
use_clock_enable                   : Yes
use_sync_set                       : Yes
use_sync_reset                     : Yes
enable_auto_floorplanning          : No

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "D:/KSC/lab2/PICunit.vhd" in Library work.
Entity <picunit> compiled.
Entity <picunit> (Architecture <behavioral>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <picunit> (Architecture <behavioral>).
Entity <picunit> analyzed. Unit <picunit> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <picunit>.
    Related source file is "D:/KSC/lab2/PICunit.vhd".
WARNING:Xst:647 - Input <TC> is never used.
    Found 1-bit register for signal <Counter_Reset>.
    Found 1-bit register for signal <EN>.
    Found 3-bit register for signal <temp_LED>.
    Summary:
	inferred   5 D-type flip-flop(s).
Unit <picunit> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Registers                        : 3
 1-bit register                    : 2
 3-bit register                    : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <picunit> ...
Loading device for application Rf_Device from file '2s50e.nph' in environment c:/xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block picunit, actual ratio is 0.

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : picunit.ngr
Top Level Output File Name         : picunit
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 14

Macro Statistics :
# Registers                        : 3
#      1-bit register              : 2
#      3-bit register              : 1

Cell Usage :
# BELS                             : 9
#      INV                         : 3
#      LUT2                        : 1
#      LUT2_L                      : 1
#      LUT4_L                      : 3
#      VCC                         : 1
# FlipFlops/Latches                : 5
#      FDCE                        : 1
#      FDR                         : 1
#      FDSE                        : 3
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 12
#      IBUF                        : 7
#      OBUF                        : 5
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s50etq144-6 

 Number of Slices:                       4  out of    768     0%  
 Number of Slice Flip Flops:             5  out of   1536     0%  
 Number of 4 input LUTs:                 5  out of   1536     0%  
 Number of bonded IOBs:                 14  out of    102    13%  
 Number of GCLKs:                        1  out of      4    25%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
PIC_clk                            | BUFGP                  | 5     |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: 3.334ns (Maximum Frequency: 299.940MHz)
   Minimum input arrival time before clock: 4.682ns
   Maximum output required time after clock: 6.744ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'PIC_clk'
  Clock period: 3.334ns (frequency: 299.940MHz)
  Total number of paths / destination ports: 4 / 4
-------------------------------------------------------------------------
Delay:               3.334ns (Levels of Logic = 1)
  Source:            temp_LED_2 (FF)
  Destination:       temp_LED_2 (FF)
  Source Clock:      PIC_clk rising
  Destination Clock: PIC_clk rising

  Data Path: temp_LED_2 to temp_LED_2
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDSE:C->Q             2   0.992   1.150  temp_LED_2 (temp_LED_2)
     LUT4_L:I0->LO         1   0.468   0.000  _n0003<2>1 (_n0003<2>)
     FDSE:D                    0.724          temp_LED_2
    ----------------------------------------
    Total                      3.334ns (2.184ns logic, 1.150ns route)
                                       (65.5% logic, 34.5% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'PIC_clk'
  Total number of paths / destination ports: 19 / 12
-------------------------------------------------------------------------
Offset:              4.682ns (Levels of Logic = 2)
  Source:            Clear (PAD)
  Destination:       temp_LED_2 (FF)
  Destination Clock: PIC_clk rising

  Data Path: Clear to temp_LED_2
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             4   0.797   1.520  Clear_IBUF (Clear_IBUF)
     INV:I->O              3   0.468   1.320  temp_LED_Sset_INV1_INV_0 (temp_LED_N0)
     FDSE:S                    0.577          temp_LED_0
    ----------------------------------------
    Total                      4.682ns (1.842ns logic, 2.840ns route)
                                       (39.3% logic, 60.7% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'PIC_clk'
  Total number of paths / destination ports: 5 / 5
-------------------------------------------------------------------------
Offset:              6.744ns (Levels of Logic = 1)
  Source:            EN (FF)
  Destination:       Counter_EN (PAD)
  Source Clock:      PIC_clk rising

  Data Path: EN to Counter_EN
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDCE:C->Q             2   0.992   1.150  EN (EN)
     OBUF:I->O                 4.602          Counter_EN_OBUF (Counter_EN)
    ----------------------------------------
    Total                      6.744ns (5.594ns logic, 1.150ns route)
                                       (82.9% logic, 17.1% route)

=========================================================================
CPU : 1.86 / 2.11 s | Elapsed : 2.00 / 2.00 s
 
--> 

Total memory usage is 86064 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :    1 (   0 filtered)
Number of infos    :    0 (   0 filtered)