microoven_translate.vhd

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    );
  u2_Qn_1 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => u2_n0002_1_Q,
      CE => u1_Key_EN,
      CLK => Clk_BUFGP,
      O => u2_Qn_1_Q,
      SET => GND,
      RST => GSR
    );
  u2_kload_3 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N195,
      CE => u1_Key_EN,
      CLK => Clk_BUFGP,
      O => u2_kload,
      SET => GND,
      RST => GSR
    );
  u2_n0002_3_1 : X_LUT4
    generic map(
      INIT => X"0880"
    )
    port map (
      ADR0 => u2_N16,
      ADR1 => u2_N14,
      ADR2 => key8_IBUF,
      ADR3 => key9_IBUF,
      O => u2_n0002_3_Q
    );
  u2_Qn_0 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N101,
      CE => u1_Key_EN,
      CLK => Clk_BUFGP,
      O => u2_Qn_0_Q,
      SET => GND,
      RST => GSR
    );
  u2_n0002_1_Q_4 : X_LUT4
    generic map(
      INIT => X"0100"
    )
    port map (
      ADR0 => key5_IBUF,
      ADR1 => key4_IBUF,
      ADR2 => N4,
      ADR3 => u2_N15,
      O => u2_n0002_1_Q
    );
  u2_Qn_2 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => u2_n0002_2_Q,
      CE => u1_Key_EN,
      CLK => Clk_BUFGP,
      O => u2_Qn_2_Q,
      SET => GND,
      RST => GSR
    );
  u2_n0002_2_Q_5 : X_LUT4
    generic map(
      INIT => X"0100"
    )
    port map (
      ADR0 => key3_IBUF,
      ADR1 => key2_IBUF,
      ADR2 => N6,
      ADR3 => u2_N15,
      O => u2_n0002_2_Q
    );
  u2_Qn_3 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => u2_n0002_3_Q,
      CE => u1_Key_EN,
      CLK => Clk_BUFGP,
      O => u2_Qn_3_Q,
      SET => GND,
      RST => GSR
    );
  u2_Ker161 : X_LUT4
    generic map(
      INIT => X"0001"
    )
    port map (
      ADR0 => key1_IBUF,
      ADR1 => key3_IBUF,
      ADR2 => key7_IBUF,
      ADR3 => key5_IBUF,
      O => u2_N16
    );
  u2_Ker141 : X_LUT4
    generic map(
      INIT => X"0001"
    )
    port map (
      ADR0 => key0_IBUF,
      ADR1 => key2_IBUF,
      ADR2 => key6_IBUF,
      ADR3 => key4_IBUF,
      O => u2_N14
    );
  u2_n0002_1_SW0 : X_LUT4
    generic map(
      INIT => X"FEE9"
    )
    port map (
      ADR0 => key7_IBUF,
      ADR1 => key6_IBUF,
      ADR2 => key3_IBUF,
      ADR3 => key2_IBUF,
      O => N4
    );
  u2_n0002_2_SW0 : X_LUT4
    generic map(
      INIT => X"FEE9"
    )
    port map (
      ADR0 => key7_IBUF,
      ADR1 => key6_IBUF,
      ADR2 => key5_IBUF,
      ADR3 => key4_IBUF,
      O => N6
    );
  u2_n000593 : X_LUT3
    generic map(
      INIT => X"06"
    )
    port map (
      ADR0 => key6_IBUF,
      ADR1 => key4_IBUF,
      ADR2 => key8_IBUF,
      O => CHOICE699
    );
  u2_n0005161 : X_LUT3
    generic map(
      INIT => X"EA"
    )
    port map (
      ADR0 => N101,
      ADR1 => u2_N16,
      ADR2 => CHOICE703,
      O => N195
    );
  H_LED_OBUF : X_BUF
    port map (
      I => u1_temp_LED_2_Q,
      O => H_LED_OBUF_GTS_TRI
    );
  u2_n0002_0_161 : X_LUT3
    generic map(
      INIT => X"08"
    )
    port map (
      ADR0 => u2_N14,
      ADR1 => CHOICE670,
      ADR2 => key8_IBUF,
      O => N101
    );
  L_LED_OBUF : X_BUF
    port map (
      I => u1_temp_LED_0_Q,
      O => L_LED_OBUF_GTS_TRI
    );
  M_LED_OBUF : X_BUF
    port map (
      I => u1_temp_LED_1_Q,
      O => M_LED_OBUF_GTS_TRI
    );
  u2_n000596 : X_LUT3
    generic map(
      INIT => X"02"
    )
    port map (
      ADR0 => CHOICE699,
      ADR1 => key0_IBUF,
      ADR2 => key2_IBUF,
      O => CHOICE700
    );
  f_OBUF_6 : X_BUF
    port map (
      I => f_OBUF,
      O => f_OBUF_GTS_TRI
    );
  u2_n000554 : X_LUT4
    generic map(
      INIT => X"0016"
    )
    port map (
      ADR0 => key2_IBUF,
      ADR1 => key0_IBUF,
      ADR2 => key8_IBUF,
      ADR3 => key6_IBUF,
      O => CHOICE688
    );
  u2_n0005127 : X_LUT4
    generic map(
      INIT => X"2232"
    )
    port map (
      ADR0 => CHOICE700,
      ADR1 => key9_IBUF,
      ADR2 => CHOICE688,
      ADR3 => key4_IBUF,
      O => CHOICE703
    );
  g_OBUF_7 : X_BUF
    port map (
      I => g_OBUF,
      O => g_OBUF_GTS_TRI
    );
  key0_IBUF_8 : X_BUF
    port map (
      I => key0,
      O => key0_IBUF
    );
  key1_IBUF_9 : X_BUF
    port map (
      I => key1,
      O => key1_IBUF
    );
  key2_IBUF_10 : X_BUF
    port map (
      I => key2,
      O => key2_IBUF
    );
  key3_IBUF_11 : X_BUF
    port map (
      I => key3,
      O => key3_IBUF
    );
  key4_IBUF_12 : X_BUF
    port map (
      I => key4,
      O => key4_IBUF
    );
  key5_IBUF_13 : X_BUF
    port map (
      I => key5,
      O => key5_IBUF
    );
  key6_IBUF_14 : X_BUF
    port map (
      I => key6,
      O => key6_IBUF
    );
  key7_IBUF_15 : X_BUF
    port map (
      I => key7,
      O => key7_IBUF
    );
  key8_IBUF_16 : X_BUF
    port map (
      I => key8,
      O => key8_IBUF
    );
  key9_IBUF_17 : X_BUF
    port map (
      I => key9,
      O => key9_IBUF
    );
  Start_IBUF_18 : X_BUF
    port map (
      I => Start,
      O => Start_IBUF
    );
  Clear_IBUF_19 : X_BUF
    port map (
      I => Clear,
      O => Clear_IBUF
    );
  Door_IBUF_20 : X_BUF
    port map (
      I => Door,
      O => Door_IBUF
    );
  Set_IBUF_21 : X_BUF
    port map (
      I => Set,
      O => Set_IBUF
    );
  a_OBUF_22 : X_BUF
    port map (
      I => a_OBUF,
      O => a_OBUF_GTS_TRI
    );
  b_OBUF_23 : X_BUF
    port map (
      I => b_OBUF,
      O => b_OBUF_GTS_TRI
    );
  c_OBUF_24 : X_BUF
    port map (
      I => c_OBUF,
      O => c_OBUF_GTS_TRI
    );
  d_OBUF_25 : X_BUF
    port map (
      I => d_OBUF,
      O => d_OBUF_GTS_TRI
    );
  e_OBUF_26 : X_BUF
    port map (
      I => e_OBUF,
      O => e_OBUF_GTS_TRI
    );
  u2_n0002_0_125_G : X_LUT4
    generic map(
      INIT => X"0001"
    )
    port map (
      ADR0 => key7_IBUF,
      ADR1 => key5_IBUF,
      ADR2 => key3_IBUF,
      ADR3 => key1_IBUF,
      O => N208
    );
  u2_n0002_0_125 : X_MUX2
    port map (
      IA => N207,
      IB => N208,
      SEL => key9_IBUF,
      O => CHOICE670
    );
  u2_n0002_0_125_F : X_LUT4
    generic map(
      INIT => X"0116"
    )
    port map (
      ADR0 => key7_IBUF,
      ADR1 => key5_IBUF,
      ADR2 => key3_IBUF,
      ADR3 => key1_IBUF,
      O => N207
    );
  u3_n00051_LUT4_L_BUF : X_BUF
    port map (
      I => u3_n00051_O,
      O => u3_N3
    );
  u3_n00051 : X_LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      ADR0 => u3_COUNT_0_Q,
      ADR1 => u3_COUNT_1_Q,
      ADR2 => u3_COUNT_2_Q,
      ADR3 => u3_COUNT_3_Q,
      O => u3_n00051_O
    );
  u3_COUNT_n0001_3_LUT4_L_BUF : X_BUF
    port map (
      I => u3_COUNT_n0001_3_O,
      O => u3_COUNT_n0001_3_Q
    );
  u3_COUNT_n0001_3_Q_52 : X_LUT4
    generic map(
      INIT => X"EB41"
    )
    port map (
      ADR0 => u2_kload,
      ADR1 => N202,
      ADR2 => u3_COUNT_3_Q,
      ADR3 => u2_Qn_3_Q,
      O => u3_COUNT_n0001_3_O
    );
  u3_COUNT_n0001_2_LUT4_L_BUF : X_BUF
    port map (
      I => u3_COUNT_n0001_2_O,
      O => u3_COUNT_n0001_2_Q
    );
  u3_COUNT_n0001_2_Q_53 : X_LUT4
    generic map(
      INIT => X"EB41"
    )
    port map (
      ADR0 => u2_kload,
      ADR1 => N200,
      ADR2 => u3_COUNT_2_Q,
      ADR3 => u2_Qn_2_Q,
      O => u3_COUNT_n0001_2_O
    );
  u3_COUNT_n0001_3_SW0_LUT3_L_BUF : X_BUF
    port map (
      I => u3_COUNT_n0001_3_SW0_O,
      O => N202
    );
  u3_COUNT_n0001_3_SW0 : X_LUT3
    generic map(
      INIT => X"FE"
    )
    port map (
      ADR0 => u3_COUNT_1_Q,
      ADR1 => u3_COUNT_0_Q,
      ADR2 => u3_COUNT_2_Q,
      O => u3_COUNT_n0001_3_SW0_O
    );
  u3_COUNT_n0001_2_SW0_LUT2_L_BUF : X_BUF
    port map (
      I => u3_COUNT_n0001_2_SW0_O,
      O => N200
    );
  u3_COUNT_n0001_2_SW0 : X_LUT2
    generic map(
      INIT => X"E"
    )
    port map (
      ADR0 => u3_COUNT_1_Q,
      ADR1 => u3_COUNT_0_Q,
      O => u3_COUNT_n0001_2_SW0_O
    );
  Clk_BUFGP_BUFG : X_CKBUF
    port map (
      I => Clk_BUFGP_IBUFG,
      O => Clk_BUFGP
    );
  Clk_BUFGP_IBUFG_54 : X_CKBUF
    port map (
      I => Clk,
      O => Clk_BUFGP_IBUFG
    );
  u3_COUNT_0_GSR_OR_55 : X_OR2
    port map (
      I0 => u3_COUNT_0_0_n0000,
      I1 => GSR,
      O => u3_COUNT_0_GSR_OR
    );
  u3_COUNT_1_GSR_OR_56 : X_OR2
    port map (
      I0 => u3_COUNT_0_1_n0000,
      I1 => GSR,
      O => u3_COUNT_1_GSR_OR
    );
  u3_COUNT_3_GSR_OR_57 : X_OR2
    port map (
      I0 => u3_COUNT_0_3_n0000,
      I1 => GSR,
      O => u3_COUNT_3_GSR_OR
    );
  u3_COUNT_2_GSR_OR_58 : X_OR2
    port map (
      I0 => u3_COUNT_0_2_n0000,
      I1 => GSR,
      O => u3_COUNT_2_GSR_OR
    );
  u1_EN_GSR_OR_59 : X_OR2
    port map (
      I0 => u1_EN_N0,
      I1 => GSR,
      O => u1_EN_GSR_OR
    );
  H_LED_OBUF_GTS_TRI_60 : X_TRI
    port map (
      I => H_LED_OBUF_GTS_TRI,
      CTL => NlwInverterSignal_H_LED_OBUF_GTS_TRI_CTL,
      O => H_LED
    );
  g_OBUF_GTS_TRI_61 : X_TRI
    port map (
      I => g_OBUF_GTS_TRI,
      CTL => NlwInverterSignal_g_OBUF_GTS_TRI_CTL,
      O => g
    );
  M_LED_OBUF_GTS_TRI_62 : X_TRI
    port map (
      I => M_LED_OBUF_GTS_TRI,
      CTL => NlwInverterSignal_M_LED_OBUF_GTS_TRI_CTL,
      O => M_LED
    );
  L_LED_OBUF_GTS_TRI_63 : X_TRI
    port map (
      I => L_LED_OBUF_GTS_TRI,
      CTL => NlwInverterSignal_L_LED_OBUF_GTS_TRI_CTL,
      O => L_LED
    );
  a_OBUF_GTS_TRI_64 : X_TRI
    port map (
      I => a_OBUF_GTS_TRI,
      CTL => NlwInverterSignal_a_OBUF_GTS_TRI_CTL,
      O => a
    );
  b_OBUF_GTS_TRI_65 : X_TRI
    port map (
      I => b_OBUF_GTS_TRI,
      CTL => NlwInverterSignal_b_OBUF_GTS_TRI_CTL,
      O => b
    );
  c_OBUF_GTS_TRI_66 : X_TRI
    port map (
      I => c_OBUF_GTS_TRI,
      CTL => NlwInverterSignal_c_OBUF_GTS_TRI_CTL,
      O => c
    );
  d_OBUF_GTS_TRI_67 : X_TRI
    port map (
      I => d_OBUF_GTS_TRI,
      CTL => NlwInverterSignal_d_OBUF_GTS_TRI_CTL,
      O => d
    );
  e_OBUF_GTS_TRI_68 : X_TRI
    port map (
      I => e_OBUF_GTS_TRI,
      CTL => NlwInverterSignal_e_OBUF_GTS_TRI_CTL,
      O => e
    );
  f_OBUF_GTS_TRI_69 : X_TRI
    port map (
      I => f_OBUF_GTS_TRI,
      CTL => NlwInverterSignal_f_OBUF_GTS_TRI_CTL,
      O => f
    );
  NlwBlock_microoven_GND : X_ZERO
    port map (
      O => GND
    );
  NlwBlock_microoven_VCC : X_ONE
    port map (
      O => VCC
    );
  NlwInverterBlock_H_LED_OBUF_GTS_TRI_CTL : X_INV
    port map (
      I => GTS,
      O => NlwInverterSignal_H_LED_OBUF_GTS_TRI_CTL
    );
  NlwInverterBlock_g_OBUF_GTS_TRI_CTL : X_INV
    port map (
      I => GTS,
      O => NlwInverterSignal_g_OBUF_GTS_TRI_CTL
    );
  NlwInverterBlock_M_LED_OBUF_GTS_TRI_CTL : X_INV
    port map (
      I => GTS,
      O => NlwInverterSignal_M_LED_OBUF_GTS_TRI_CTL
    );
  NlwInverterBlock_L_LED_OBUF_GTS_TRI_CTL : X_INV
    port map (
      I => GTS,
      O => NlwInverterSignal_L_LED_OBUF_GTS_TRI_CTL
    );
  NlwInverterBlock_a_OBUF_GTS_TRI_CTL : X_INV
    port map (
      I => GTS,
      O => NlwInverterSignal_a_OBUF_GTS_TRI_CTL
    );
  NlwInverterBlock_b_OBUF_GTS_TRI_CTL : X_INV
    port map (
      I => GTS,
      O => NlwInverterSignal_b_OBUF_GTS_TRI_CTL
    );
  NlwInverterBlock_c_OBUF_GTS_TRI_CTL : X_INV
    port map (
      I => GTS,
      O => NlwInverterSignal_c_OBUF_GTS_TRI_CTL
    );
  NlwInverterBlock_d_OBUF_GTS_TRI_CTL : X_INV
    port map (
      I => GTS,
      O => NlwInverterSignal_d_OBUF_GTS_TRI_CTL
    );
  NlwInverterBlock_e_OBUF_GTS_TRI_CTL : X_INV
    port map (
      I => GTS,
      O => NlwInverterSignal_e_OBUF_GTS_TRI_CTL
    );
  NlwInverterBlock_f_OBUF_GTS_TRI_CTL : X_INV
    port map (
      I => GTS,
      O => NlwInverterSignal_f_OBUF_GTS_TRI_CTL
    );
  NlwBlockROC : X_ROC
    generic map (ROC_WIDTH => 100 ns)
    port map (O => GSR);
  NlwBlockTOC : X_TOC
    port map (O => GTS);

end Structure;