microoven_translate.vhd

微波爐．．．．．．．．．．．．．．．．．．．．．．．．．．

--------------------------------------------------------------------------------
-- Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.
--------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor: Xilinx
-- \   \   \/     Version: H.42
--  \   \         Application: netgen
--  /   /         Filename: microoven_translate.vhd
-- /___/   /\     Timestamp: Tue Mar 10 15:44:52 2009
-- \   \  /  \ 
--  \___\/\___\
--             
-- Command	: -intstyle ise -rpw 100 -tpw 0 -ar Structure -xon true -w -ofmt vhdl -sim microoven.ngd microoven_translate.vhd 
-- Device	: 2s50etq144-6
-- Input file	: microoven.ngd
-- Output file	: microoven_translate.vhd
-- # of Entities	: 1
-- Design Name	: microoven
-- Xilinx	: c:/xilinx
--             
-- Purpose:    
--     This VHDL netlist is a verification model and uses simulation 
--     primitives which may not represent the true implementation of the 
--     device, however the netlist is functionally correct and should not 
--     be modified. This file cannot be synthesized and should only be used 
--     with supported simulation tools.
--             
-- Reference:  
--     Development System Reference Guide, Chapter 23
--     Synthesis and Verification Design Guide, Chapter 6
--             
--------------------------------------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library SIMPRIM;
use SIMPRIM.VCOMPONENTS.ALL;
use SIMPRIM.VPACKAGE.ALL;

entity microoven is
  port (
    Clk : in STD_LOGIC := 'X'; 
    key0 : in STD_LOGIC := 'X'; 
    key1 : in STD_LOGIC := 'X'; 
    key2 : in STD_LOGIC := 'X'; 
    key3 : in STD_LOGIC := 'X'; 
    key4 : in STD_LOGIC := 'X'; 
    key5 : in STD_LOGIC := 'X'; 
    key6 : in STD_LOGIC := 'X'; 
    key7 : in STD_LOGIC := 'X'; 
    key8 : in STD_LOGIC := 'X'; 
    key9 : in STD_LOGIC := 'X'; 
    Start : in STD_LOGIC := 'X'; 
    Clear : in STD_LOGIC := 'X'; 
    Door : in STD_LOGIC := 'X'; 
    Set : in STD_LOGIC := 'X'; 
    a : out STD_LOGIC; 
    b : out STD_LOGIC; 
    c : out STD_LOGIC; 
    d : out STD_LOGIC; 
    e : out STD_LOGIC; 
    f : out STD_LOGIC; 
    g : out STD_LOGIC; 
    L_LED : out STD_LOGIC; 
    H_LED : out STD_LOGIC; 
    M_LED : out STD_LOGIC 
  );
end microoven;

architecture Structure of microoven is
  signal Clk_BUFGP : STD_LOGIC; 
  signal key0_IBUF : STD_LOGIC; 
  signal key1_IBUF : STD_LOGIC; 
  signal key2_IBUF : STD_LOGIC; 
  signal key3_IBUF : STD_LOGIC; 
  signal key4_IBUF : STD_LOGIC; 
  signal key5_IBUF : STD_LOGIC; 
  signal key6_IBUF : STD_LOGIC; 
  signal key7_IBUF : STD_LOGIC; 
  signal key8_IBUF : STD_LOGIC; 
  signal key9_IBUF : STD_LOGIC; 
  signal Start_IBUF : STD_LOGIC; 
  signal Clear_IBUF : STD_LOGIC; 
  signal a_OBUF : STD_LOGIC; 
  signal b_OBUF : STD_LOGIC; 
  signal c_OBUF : STD_LOGIC; 
  signal d_OBUF : STD_LOGIC; 
  signal e_OBUF : STD_LOGIC; 
  signal f_OBUF : STD_LOGIC; 
  signal g_OBUF : STD_LOGIC; 
  signal u1_temp_LED_0_Q : STD_LOGIC; 
  signal u1_temp_LED_2_Q : STD_LOGIC; 
  signal Door_IBUF : STD_LOGIC; 
  signal u1_temp_LED_1_Q : STD_LOGIC; 
  signal Set_IBUF : STD_LOGIC; 
  signal u1_Key_EN : STD_LOGIC; 
  signal u2_Qn_0_Q : STD_LOGIC; 
  signal u1_Counter_Reset : STD_LOGIC; 
  signal u1_EN : STD_LOGIC; 
  signal u3_COUNT_3_Q : STD_LOGIC; 
  signal N0 : STD_LOGIC; 
  signal u2_Qn_1_Q : STD_LOGIC; 
  signal u2_Qn_3_Q : STD_LOGIC; 
  signal u2_Qn_2_Q : STD_LOGIC; 
  signal u3_COUNT_1_Q : STD_LOGIC; 
  signal u2_kload : STD_LOGIC; 
  signal u3_COUNT_0_Q : STD_LOGIC; 
  signal u3_COUNT_0_3_n0001 : STD_LOGIC; 
  signal u3_COUNT_2_Q : STD_LOGIC; 
  signal N1 : STD_LOGIC; 
  signal u3_COUNT_n0001_0_Q : STD_LOGIC; 
  signal u3_COUNT_n0001_1_Q : STD_LOGIC; 
  signal u3_COUNT_0_1_n0001 : STD_LOGIC; 
  signal u3_COUNT_0_2_n0001 : STD_LOGIC; 
  signal u3_COUNT_0_3_n0000 : STD_LOGIC; 
  signal u3_COUNT_n0001_2_Q : STD_LOGIC; 
  signal u3_COUNT_n0001_3_Q : STD_LOGIC; 
  signal u3_n0005 : STD_LOGIC; 
  signal u3_COUNT_0_0_n0000 : STD_LOGIC; 
  signal u3_COUNT_0_0_n0001 : STD_LOGIC; 
  signal u3_COUNT_0_2_n0000 : STD_LOGIC; 
  signal u3_COUNT_0_1_n0000 : STD_LOGIC; 
  signal u3_N3 : STD_LOGIC; 
  signal u1_temp_LED_N1 : STD_LOGIC; 
  signal u1_EN_N0 : STD_LOGIC; 
  signal u1_temp_LED_N0 : STD_LOGIC; 
  signal u1_n0005 : STD_LOGIC; 
  signal u1_n0006_2_Q : STD_LOGIC; 
  signal u1_n0006_0_Q : STD_LOGIC; 
  signal u1_n0006_1_Q : STD_LOGIC; 
  signal u1_EN_N1 : STD_LOGIC; 
  signal u1_n0004 : STD_LOGIC; 
  signal u2_N14 : STD_LOGIC; 
  signal u2_n0002_1_Q : STD_LOGIC; 
  signal u2_N15 : STD_LOGIC; 
  signal CHOICE703 : STD_LOGIC; 
  signal u2_N16 : STD_LOGIC; 
  signal u2_n0002_2_Q : STD_LOGIC; 
  signal N202 : STD_LOGIC; 
  signal u2_n0002_3_Q : STD_LOGIC; 
  signal N4 : STD_LOGIC; 
  signal N6 : STD_LOGIC; 
  signal N195 : STD_LOGIC; 
  signal CHOICE699 : STD_LOGIC; 
  signal N200 : STD_LOGIC; 
  signal CHOICE688 : STD_LOGIC; 
  signal N101 : STD_LOGIC; 
  signal CHOICE700 : STD_LOGIC; 
  signal CHOICE670 : STD_LOGIC; 
  signal N207 : STD_LOGIC; 
  signal N208 : STD_LOGIC; 
  signal u3_n00051_O : STD_LOGIC; 
  signal u3_COUNT_n0001_3_O : STD_LOGIC; 
  signal u3_COUNT_n0001_2_O : STD_LOGIC; 
  signal u3_COUNT_n0001_3_SW0_O : STD_LOGIC; 
  signal u3_COUNT_n0001_2_SW0_O : STD_LOGIC; 
  signal Clk_BUFGP_IBUFG : STD_LOGIC; 
  signal GSR : STD_LOGIC; 
  signal u3_COUNT_0_GSR_OR : STD_LOGIC; 
  signal u3_COUNT_1_GSR_OR : STD_LOGIC; 
  signal u3_COUNT_3_GSR_OR : STD_LOGIC; 
  signal u3_COUNT_2_GSR_OR : STD_LOGIC; 
  signal u1_EN_GSR_OR : STD_LOGIC; 
  signal H_LED_OBUF_GTS_TRI : STD_LOGIC; 
  signal GTS : STD_LOGIC; 
  signal g_OBUF_GTS_TRI : STD_LOGIC; 
  signal M_LED_OBUF_GTS_TRI : STD_LOGIC; 
  signal L_LED_OBUF_GTS_TRI : STD_LOGIC; 
  signal a_OBUF_GTS_TRI : STD_LOGIC; 
  signal b_OBUF_GTS_TRI : STD_LOGIC; 
  signal c_OBUF_GTS_TRI : STD_LOGIC; 
  signal d_OBUF_GTS_TRI : STD_LOGIC; 
  signal e_OBUF_GTS_TRI : STD_LOGIC; 
  signal f_OBUF_GTS_TRI : STD_LOGIC; 
  signal GND : STD_LOGIC; 
  signal VCC : STD_LOGIC; 
  signal NlwInverterSignal_H_LED_OBUF_GTS_TRI_CTL : STD_LOGIC; 
  signal NlwInverterSignal_g_OBUF_GTS_TRI_CTL : STD_LOGIC; 
  signal NlwInverterSignal_M_LED_OBUF_GTS_TRI_CTL : STD_LOGIC; 
  signal NlwInverterSignal_L_LED_OBUF_GTS_TRI_CTL : STD_LOGIC; 
  signal NlwInverterSignal_a_OBUF_GTS_TRI_CTL : STD_LOGIC; 
  signal NlwInverterSignal_b_OBUF_GTS_TRI_CTL : STD_LOGIC; 
  signal NlwInverterSignal_c_OBUF_GTS_TRI_CTL : STD_LOGIC; 
  signal NlwInverterSignal_d_OBUF_GTS_TRI_CTL : STD_LOGIC; 
  signal NlwInverterSignal_e_OBUF_GTS_TRI_CTL : STD_LOGIC; 
  signal NlwInverterSignal_f_OBUF_GTS_TRI_CTL : STD_LOGIC; 
begin
  XST_GND : X_ZERO
    port map (
      O => N0
    );
  u5_Mrom_output_inst_lut4_61 : X_LUT4
    generic map(
      INIT => X"2812"
    )
    port map (
      ADR0 => u3_COUNT_0_Q,
      ADR1 => u3_COUNT_1_Q,
      ADR2 => u3_COUNT_2_Q,
      ADR3 => u3_COUNT_3_Q,
      O => g_OBUF
    );
  u3_COUNT_0_n00011 : X_LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      ADR0 => u2_Qn_0_Q,
      ADR1 => u2_kload,
      O => u3_COUNT_0_0_n0001
    );
  u2_Ker151 : X_LUT4
    generic map(
      INIT => X"0001"
    )
    port map (
      ADR0 => key8_IBUF,
      ADR1 => key9_IBUF,
      ADR2 => key0_IBUF,
      ADR3 => key1_IBUF,
      O => u2_N15
    );
  u1_EN_Aclr_INV1_INV_0 : X_INV
    port map (
      I => Door_IBUF,
      O => u1_EN_N0
    );
  XST_VCC : X_ONE
    port map (
      O => N1
    );
  u5_Mrom_output_inst_lut4_01 : X_LUT4
    generic map(
      INIT => X"1083"
    )
    port map (
      ADR0 => u3_COUNT_0_Q,
      ADR1 => u3_COUNT_1_Q,
      ADR2 => u3_COUNT_2_Q,
      ADR3 => u3_COUNT_3_Q,
      O => a_OBUF
    );
  u5_Mrom_output_inst_lut4_11 : X_LUT4
    generic map(
      INIT => X"6032"
    )
    port map (
      ADR0 => u3_COUNT_1_Q,
      ADR1 => u3_COUNT_3_Q,
      ADR2 => u3_COUNT_0_Q,
      ADR3 => u3_COUNT_2_Q,
      O => b_OBUF
    );
  u5_Mrom_output_inst_lut4_21 : X_LUT4
    generic map(
      INIT => X"10F4"
    )
    port map (
      ADR0 => u3_COUNT_1_Q,
      ADR1 => u3_COUNT_2_Q,
      ADR2 => u3_COUNT_0_Q,
      ADR3 => u3_COUNT_3_Q,
      O => c_OBUF
    );
  u5_Mrom_output_inst_lut4_31 : X_LUT4
    generic map(
      INIT => X"8492"
    )
    port map (
      ADR0 => u3_COUNT_0_Q,
      ADR1 => u3_COUNT_1_Q,
      ADR2 => u3_COUNT_2_Q,
      ADR3 => u3_COUNT_3_Q,
      O => d_OBUF
    );
  u5_Mrom_output_inst_lut4_41 : X_LUT4
    generic map(
      INIT => X"8098"
    )
    port map (
      ADR0 => u3_COUNT_2_Q,
      ADR1 => u3_COUNT_3_Q,
      ADR2 => u3_COUNT_1_Q,
      ADR3 => u3_COUNT_0_Q,
      O => e_OBUF
    );
  u5_Mrom_output_inst_lut4_51 : X_LUT4
    generic map(
      INIT => X"D680"
    )
    port map (
      ADR0 => u3_COUNT_0_Q,
      ADR1 => u3_COUNT_1_Q,
      ADR2 => u3_COUNT_3_Q,
      ADR3 => u3_COUNT_2_Q,
      O => f_OBUF
    );
  u3_COUNT_1_n00011 : X_LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      ADR0 => u2_Qn_1_Q,
      ADR1 => u2_kload,
      O => u3_COUNT_0_1_n0001
    );
  u3_COUNT_0 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => u3_COUNT_n0001_0_Q,
      CE => u3_n0005,
      RST => u3_COUNT_0_GSR_OR,
      SET => u3_COUNT_0_0_n0001,
      CLK => Clk_BUFGP,
      O => u3_COUNT_0_Q
    );
  u3_COUNT_1 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => u3_COUNT_n0001_1_Q,
      CE => u3_n0005,
      RST => u3_COUNT_1_GSR_OR,
      SET => u3_COUNT_0_1_n0001,
      CLK => Clk_BUFGP,
      O => u3_COUNT_1_Q
    );
  u3_COUNT_n0001_0_1 : X_LUT3
    generic map(
      INIT => X"B1"
    )
    port map (
      ADR0 => u2_kload,
      ADR1 => u3_COUNT_0_Q,
      ADR2 => u2_Qn_0_Q,
      O => u3_COUNT_n0001_0_Q
    );
  u3_COUNT_2_n00011 : X_LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      ADR0 => u2_Qn_2_Q,
      ADR1 => u2_kload,
      O => u3_COUNT_0_2_n0001
    );
  u3_n00052 : X_LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      ADR0 => u1_EN,
      ADR1 => u3_N3,
      O => u3_n0005
    );
  u3_COUNT_n0001_1_1 : X_LUT4
    generic map(
      INIT => X"EB41"
    )
    port map (
      ADR0 => u2_kload,
      ADR1 => u3_COUNT_0_Q,
      ADR2 => u3_COUNT_1_Q,
      ADR3 => u2_Qn_1_Q,
      O => u3_COUNT_n0001_1_Q
    );
  u3_COUNT_3_n00011 : X_LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      ADR0 => u2_Qn_3_Q,
      ADR1 => u2_kload,
      O => u3_COUNT_0_3_n0001
    );
  u3_COUNT_1_n00001 : X_LUT3
    generic map(
      INIT => X"F4"
    )
    port map (
      ADR0 => u2_Qn_1_Q,
      ADR1 => u2_kload,
      ADR2 => u1_Counter_Reset,
      O => u3_COUNT_0_1_n0000
    );
  u3_COUNT_0_n00001 : X_LUT3
    generic map(
      INIT => X"F4"
    )
    port map (
      ADR0 => u2_Qn_0_Q,
      ADR1 => u2_kload,
      ADR2 => u1_Counter_Reset,
      O => u3_COUNT_0_0_n0000
    );
  u3_COUNT_2_n00001 : X_LUT3
    generic map(
      INIT => X"F4"
    )
    port map (
      ADR0 => u2_Qn_2_Q,
      ADR1 => u2_kload,
      ADR2 => u1_Counter_Reset,
      O => u3_COUNT_0_2_n0000
    );
  u3_COUNT_3 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => u3_COUNT_n0001_3_Q,
      CE => u3_n0005,
      RST => u3_COUNT_3_GSR_OR,
      SET => u3_COUNT_0_3_n0001,
      CLK => Clk_BUFGP,
      O => u3_COUNT_3_Q
    );
  u3_COUNT_3_n00001 : X_LUT3
    generic map(
      INIT => X"F4"
    )
    port map (
      ADR0 => u2_Qn_3_Q,
      ADR1 => u2_kload,
      ADR2 => u1_Counter_Reset,
      O => u3_COUNT_0_3_n0000
    );
  u3_COUNT_2 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => u3_COUNT_n0001_2_Q,
      CE => u3_n0005,
      RST => u3_COUNT_2_GSR_OR,
      SET => u3_COUNT_0_2_n0001,
      CLK => Clk_BUFGP,
      O => u3_COUNT_2_Q
    );
  u1_temp_LED_2 : X_SFF
    generic map(
      INIT => '1'
    )
    port map (
      I => u1_n0006_2_Q,
      SSET => u1_temp_LED_N0,
      CE => u1_temp_LED_N1,
      CLK => Clk_BUFGP,
      O => u1_temp_LED_2_Q,
      SET => GSR,
      RST => GND,
      SRST => GND
    );
  u1_Counter_Reset_0 : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => N1,
      SRST => Clear_IBUF,
      CLK => Clk_BUFGP,
      O => u1_Counter_Reset,
      CE => VCC,
      SET => GND,
      RST => GSR,
      SSET => GND
    );
  u1_Key_EN_1 : X_SFF
    generic map(
      INIT => '1'
    )
    port map (
      I => N0,
      SSET => u1_n0005,
      CLK => Clk_BUFGP,
      O => u1_Key_EN,
      CE => VCC,
      SET => GSR,
      RST => GND,
      SRST => GND
    );
  u1_EN_2 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => u1_n0004,
      CE => u1_EN_N1,
      RST => u1_EN_GSR_OR,
      CLK => Clk_BUFGP,
      O => u1_EN,
      SET => GND
    );
  u1_temp_LED_Sset_INV1_INV_0 : X_INV
    port map (
      I => Clear_IBUF,
      O => u1_temp_LED_N0
    );
  u1_temp_LED_1 : X_SFF
    generic map(
      INIT => '1'
    )
    port map (
      I => u1_n0006_1_Q,
      SSET => u1_temp_LED_N0,
      CE => u1_temp_LED_N1,
      CLK => Clk_BUFGP,
      O => u1_temp_LED_1_Q,
      SET => GSR,
      RST => GND,
      SRST => GND
    );
  u1_temp_LED_ClkEn_INV1_INV_0 : X_INV
    port map (
      I => Set_IBUF,
      O => u1_temp_LED_N1
    );
  u1_n00041 : X_LUT2
    generic map(
      INIT => X"2"
    )
    port map (
      ADR0 => Clear_IBUF,
      ADR1 => u1_EN,
      O => u1_n0004
    );
  u1_temp_LED_0 : X_SFF
    generic map(
      INIT => '1'
    )
    port map (
      I => u1_n0006_0_Q,
      SSET => u1_temp_LED_N0,
      CE => u1_temp_LED_N1,
      CLK => Clk_BUFGP,
      O => u1_temp_LED_0_Q,
      SET => GSR,
      RST => GND,
      SRST => GND
    );
  u1_n00051 : X_LUT2
    generic map(
      INIT => X"B"
    )
    port map (
      ADR0 => Set_IBUF,
      ADR1 => Clear_IBUF,
      O => u1_n0005
    );
  u1_n0006_2_1 : X_LUT4
    generic map(
      INIT => X"AB8E"
    )
    port map (
      ADR0 => u1_temp_LED_2_Q,
      ADR1 => key8_IBUF,
      ADR2 => key9_IBUF,
      ADR3 => key7_IBUF,
      O => u1_n0006_2_Q
    );
  u1_n0006_1_1 : X_LUT4
    generic map(
      INIT => X"AB8E"
    )
    port map (
      ADR0 => u1_temp_LED_1_Q,
      ADR1 => key7_IBUF,
      ADR2 => key8_IBUF,
      ADR3 => key9_IBUF,
      O => u1_n0006_1_Q
    );
  u1_n0006_0_1 : X_LUT4
    generic map(
      INIT => X"AB8E"
    )
    port map (
      ADR0 => u1_temp_LED_0_Q,
      ADR1 => key8_IBUF,
      ADR2 => key7_IBUF,
      ADR3 => key9_IBUF,
      O => u1_n0006_0_Q
    );
  u1_EN_ClkEn_INV1 : X_LUT2
    generic map(
      INIT => X"7"
    )
    port map (
      ADR0 => Clear_IBUF,
      ADR1 => Start_IBUF,
      O => u1_EN_N1