clkdiv2.vhd

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-- Company: 
-- Engineer:
--
-- Create Date:    11:13:23 02/16/09
-- Design Name:    
-- Module Name:    clkdiv2 - Behavioral
-- Project Name:   
-- Target Device:  
-- Tool versions:  
-- Description:
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity clkdiv2 is
    Port (
		clkin : in std_logic;
		clkoutsec : out std_logic
	 );
end clkdiv2;

architecture Behavioral of clkdiv2 is

constant timefix : integer := 50;
signal counta, countb, countc, countd : integer range 0 to 51;
signal B : std_logic := '0';

begin

	process (clkin,B)
		begin
			if rising_edge(clkin) then
				counta <= counta + 1;
				if counta = timefix then
					counta <= 0;
					countb <= countb + 1;
				elsif countb = timefix then
					countb <= 0;
					countc <= countc + 1;
				elsif countc = timefix then
					countc <= 0;
					countd <= countd + 1;
				elsif countd = timefix then
					countd <= 0;
					B <= not B;
				end if;
			end if;
			clkoutsec <= B;
	end process;

end Behavioral;