microoven_synthesis.vhd

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    );
  u3_COUNT_n0001_3_SW0 : LUT3_L
    generic map(
      INIT => X"FE"
    )
    port map (
      I0 => u3_COUNT_1_Q,
      I1 => u3_COUNT_0_Q,
      I2 => u3_COUNT_2_Q,
      LO => N230
    );
  u3_COUNT_n0001_2_SW0 : LUT2_L
    generic map(
      INIT => X"E"
    )
    port map (
      I0 => u3_COUNT_1_Q,
      I1 => u3_COUNT_0_Q,
      LO => N228
    );
  u2_n0002_3_1 : LUT4
    generic map(
      INIT => X"0880"
    )
    port map (
      I0 => u2_N16,
      I1 => u2_N14,
      I2 => key8_IBUF,
      I3 => key9_IBUF,
      O => u2_n0002_3_Q
    );
  u2_Qn_0 : FDE
    port map (
      D => N104,
      CE => Set_IBUF,
      C => u4_B,
      Q => u2_Qn_0_Q
    );
  u2_n0002_1_Q_40 : LUT4
    generic map(
      INIT => X"0100"
    )
    port map (
      I0 => key5_IBUF,
      I1 => key4_IBUF,
      I2 => N7,
      I3 => u2_N15,
      O => u2_n0002_1_Q
    );
  u2_Qn_2 : FDE
    port map (
      D => u2_n0002_2_Q,
      CE => Set_IBUF,
      C => u4_B,
      Q => u2_Qn_2_Q
    );
  u2_n0002_2_Q_41 : LUT4
    generic map(
      INIT => X"0100"
    )
    port map (
      I0 => key3_IBUF,
      I1 => key2_IBUF,
      I2 => N9,
      I3 => u2_N15,
      O => u2_n0002_2_Q
    );
  u2_Qn_3 : FDE
    port map (
      D => u2_n0002_3_Q,
      CE => Set_IBUF,
      C => u4_B,
      Q => u2_Qn_3_Q
    );
  u2_Ker161 : LUT4
    generic map(
      INIT => X"0001"
    )
    port map (
      I0 => key1_IBUF,
      I1 => key3_IBUF,
      I2 => key7_IBUF,
      I3 => key5_IBUF,
      O => u2_N16
    );
  u2_Ker141 : LUT4
    generic map(
      INIT => X"0001"
    )
    port map (
      I0 => key0_IBUF,
      I1 => key2_IBUF,
      I2 => key6_IBUF,
      I3 => key4_IBUF,
      O => u2_N14
    );
  u1_n0004_SW0 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => u3_COUNT_3_Q,
      I1 => u3_COUNT_2_Q,
      O => N5
    );
  u2_n0002_1_SW0 : LUT4
    generic map(
      INIT => X"FEE9"
    )
    port map (
      I0 => key7_IBUF,
      I1 => key6_IBUF,
      I2 => key3_IBUF,
      I3 => key2_IBUF,
      O => N7
    );
  u2_n0002_2_SW0 : LUT4
    generic map(
      INIT => X"FEE9"
    )
    port map (
      I0 => key7_IBUF,
      I1 => key6_IBUF,
      I2 => key5_IBUF,
      I3 => key4_IBUF,
      O => N9
    );
  u4_n0005_SW0 : LUT3_L
    generic map(
      INIT => X"F7"
    )
    port map (
      I0 => u4_counta_4_Q,
      I1 => u4_counta_5_Q,
      I2 => u4_counta_3_Q,
      LO => N226
    );
  u4_n0011_SW0 : LUT3_L
    generic map(
      INIT => X"F7"
    )
    port map (
      I0 => u4_countb_4_Q,
      I1 => u4_countb_5_Q,
      I2 => u4_countb_3_Q,
      LO => N224
    );
  u4_n0012_SW0 : LUT3_L
    generic map(
      INIT => X"F7"
    )
    port map (
      I0 => u4_countc_4_Q,
      I1 => u4_countc_5_Q,
      I2 => u4_countc_3_Q,
      LO => N222
    );
  u4_n0021_SW0 : LUT3
    generic map(
      INIT => X"F7"
    )
    port map (
      I0 => u4_countd_4_Q,
      I1 => u4_countd_5_Q,
      I2 => u4_countd_3_Q,
      O => N220
    );
  u6_n0005_SW0 : LUT2_L
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => u6_counta_3_Q,
      I1 => u6_counta_4_Q,
      LO => N218
    );
  u6_n0011_SW0 : LUT2_L
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => u6_countb_3_Q,
      I1 => u6_countb_4_Q,
      LO => N216
    );
  u6_n0012_SW0 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => u6_countc_3_Q,
      I1 => u6_countc_4_Q,
      O => N214
    );
  u6_n0021_SW0 : LUT2_L
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => u6_countd_3_Q,
      I1 => u6_countd_4_Q,
      LO => N212
    );
  u2_n000593 : LUT3
    generic map(
      INIT => X"06"
    )
    port map (
      I0 => key6_IBUF,
      I1 => key4_IBUF,
      I2 => key8_IBUF,
      O => CHOICE704
    );
  u2_n0005161 : LUT3
    generic map(
      INIT => X"EA"
    )
    port map (
      I0 => N104,
      I1 => u2_N16,
      I2 => CHOICE708,
      O => N198
    );
  u4_counta_5_rt_42 : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => u4_counta_5_Q,
      O => u4_counta_5_rt
    );
  u2_n000554 : LUT4
    generic map(
      INIT => X"0016"
    )
    port map (
      I0 => key2_IBUF,
      I1 => key0_IBUF,
      I2 => key8_IBUF,
      I3 => key6_IBUF,
      O => CHOICE693
    );
  u6_counta_4_rt_43 : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => u6_counta_4_Q,
      O => u6_counta_4_rt
    );
  u2_n0002_0_161 : LUT3
    generic map(
      INIT => X"08"
    )
    port map (
      I0 => u2_N14,
      I1 => CHOICE675,
      I2 => key8_IBUF,
      O => N104
    );
  u2_n000596 : LUT3
    generic map(
      INIT => X"02"
    )
    port map (
      I0 => CHOICE704,
      I1 => key0_IBUF,
      I2 => key2_IBUF,
      O => CHOICE705
    );
  u4_n0008_0_2 : LUT4
    generic map(
      INIT => X"0100"
    )
    port map (
      I0 => u4_countd_0_Q,
      I1 => u4_countc_0_Q,
      I2 => u4_N19,
      I3 => u4_countc_1_Q,
      O => u4_n0008_0_Q
    );
  u4_countd_5_rt_44 : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => u4_countd_5_Q,
      O => u4_countd_5_rt
    );
  u2_n0005127 : LUT4
    generic map(
      INIT => X"2232"
    )
    port map (
      I0 => CHOICE705,
      I1 => key9_IBUF,
      I2 => CHOICE693,
      I3 => key4_IBUF,
      O => CHOICE708
    );
  u6_countd_1_rt_45 : LUT1_L
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => u6_countd_1_Q,
      LO => u6_countd_1_rt
    );
  u6_countd_2_rt_46 : LUT1_L
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => u6_countd_2_Q,
      LO => u6_countd_2_rt
    );
  u6_countd_3_rt_47 : LUT1_L
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => u6_countd_3_Q,
      LO => u6_countd_3_rt
    );
  u6_countc_1_rt_48 : LUT1_L
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => u6_countc_1_Q,
      LO => u6_countc_1_rt
    );
  u6_countc_2_rt_49 : LUT1_L
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => u6_countc_2_Q,
      LO => u6_countc_2_rt
    );
  u6_countc_3_rt_50 : LUT1_L
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => u6_countc_3_Q,
      LO => u6_countc_3_rt
    );
  u6_countb_1_rt_51 : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => u6_countb_1_Q,
      O => u6_countb_1_rt
    );
  u6_countb_2_rt_52 : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => u6_countb_2_Q,
      O => u6_countb_2_rt
    );
  u6_countb_3_rt_53 : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => u6_countb_3_Q,
      O => u6_countb_3_rt
    );
  u6_counta_3_rt_54 : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => u6_counta_3_Q,
      O => u6_counta_3_rt
    );
  u6_counta_1_rt_55 : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => u6_counta_1_Q,
      O => u6_counta_1_rt
    );
  u6_counta_2_rt_56 : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => u6_counta_2_Q,
      O => u6_counta_2_rt
    );
  u4_countd_1_rt_57 : LUT1_L
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => u4_countd_1_Q,
      LO => u4_countd_1_rt
    );
  u4_countd_2_rt_58 : LUT1_L
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => u4_countd_2_Q,
      LO => u4_countd_2_rt
    );
  u4_countd_3_rt_59 : LUT1_L
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => u4_countd_3_Q,
      LO => u4_countd_3_rt
    );
  u4_countd_4_rt_60 : LUT1_L
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => u4_countd_4_Q,
      LO => u4_countd_4_rt
    );
  u4_countc_1_rt_61 : LUT1_L
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => u4_countc_1_Q,
      LO => u4_countc_1_rt
    );
  u4_countc_2_rt_62 : LUT1_L
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => u4_countc_2_Q,
      LO => u4_countc_2_rt
    );
  u4_countc_3_rt_63 : LUT1_L
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => u4_countc_3_Q,
      LO => u4_countc_3_rt
    );
  u4_countc_4_rt_64 : LUT1_L
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => u4_countc_4_Q,
      LO => u4_countc_4_rt
    );
  u4_countb_1_rt_65 : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => u4_countb_1_Q,
      O => u4_countb_1_rt
    );
  u4_countb_2_rt_66 : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => u4_countb_2_Q,
      O => u4_countb_2_rt
    );
  u4_countb_3_rt_67 : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => u4_countb_3_Q,
      O => u4_countb_3_rt
    );
  u4_countb_4_rt_68 : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => u4_countb_4_Q,
      O => u4_countb_4_rt
    );
  u4_counta_4_rt_69 : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => u4_counta_4_Q,
      O => u4_counta_4_rt
    );
  u4_counta_1_rt_70 : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => u4_counta_1_Q,
      O => u4_counta_1_rt
    );
  u4_counta_2_rt_71 : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => u4_counta_2_Q,
      O => u4_counta_2_rt
    );
  u4_counta_3_rt_72 : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => u4_counta_3_Q,
      O => u4_counta_3_rt
    );
  u6_countd_4_rt_73 : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => u6_countd_4_Q,
      O => u6_countd_4_rt
    );
  u6_countc_4_rt_74 : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => u6_countc_4_Q,
      O => u6_countc_4_rt
    );
  u6_countb_4_rt_75 : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => u6_countb_4_Q,
      O => u6_countb_4_rt
    );
  u2_n0002_0_125_G : LUT4
    generic map(
      INIT => X"0001"
    )
    port map (
      I0 => key7_IBUF,
      I1 => key5_IBUF,
      I2 => key3_IBUF,
      I3 => key1_IBUF,
      O => N238
    );
  u2_n0002_0_125 : MUXF5
    port map (
      I0 => N237,
      I1 => N238,
      S => key9_IBUF,
      O => CHOICE675
    );
  u2_n0002_0_125_F : LUT4
    generic map(
      INIT => X"0116"
    )
    port map (
      I0 => key7_IBUF,
      I1 => key5_IBUF,
      I2 => key3_IBUF,
      I3 => key1_IBUF,
      O => N237
    );

end Structure;