microoven_synthesis.vhd

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      D => u4_countb_n0000_1_Q,
      R => u4_n0006,
      CE => u4_n0005,
      C => Clk_BUFGP,
      Q => u4_countb_1_Q
    );
  u4_countb_2 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      D => u4_countb_n0000_2_Q,
      R => u4_n0006,
      CE => u4_n0005,
      C => Clk_BUFGP,
      Q => u4_countb_2_Q
    );
  u4_countb_3 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      D => u4_countb_n0000_3_Q,
      R => u4_n0006,
      CE => u4_n0005,
      C => Clk_BUFGP,
      Q => u4_countb_3_Q
    );
  u4_counta_5 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      D => u4_counta_n0000_5_Q,
      R => u4_n0005,
      C => Clk_BUFGP,
      Q => u4_counta_5_Q
    );
  u4_clkdiv2_counta_n0000_5_xor : XORCY
    port map (
      CI => u4_clkdiv2_counta_n0000_4_cyo,
      LI => u4_counta_5_rt,
      O => u4_counta_n0000_5_Q
    );
  u4_counta_0 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      D => u4_N9,
      R => u4_n0005,
      C => Clk_BUFGP,
      Q => u4_counta_0_Q
    );
  u4_counta_1 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      D => u4_counta_n0000_1_Q,
      R => u4_n0005,
      C => Clk_BUFGP,
      Q => u4_counta_1_Q
    );
  u4_counta_2 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      D => u4_counta_n0000_2_Q,
      R => u4_n0005,
      C => Clk_BUFGP,
      Q => u4_counta_2_Q
    );
  u4_counta_3 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      D => u4_counta_n0000_3_Q,
      R => u4_n0005,
      C => Clk_BUFGP,
      Q => u4_counta_3_Q
    );
  key7_IBUF_30 : IBUF
    port map (
      I => key7,
      O => key7_IBUF
    );
  u4_n0008_4_2 : LUT4_L
    generic map(
      INIT => X"0020"
    )
    port map (
      I0 => u4_n0010_4_Q,
      I1 => u4_countc_0_Q,
      I2 => u4_countc_1_Q,
      I3 => u4_N19,
      LO => u4_n0008_4_Q
    );
  u4_clkdiv2_n0010_0_lut_INV_0 : INV
    port map (
      I => u4_countd_0_Q,
      O => u4_N6
    );
  u4_clkdiv2_n0010_0_cy : MUXCY
    port map (
      CI => N0,
      DI => N1,
      S => u4_N6,
      O => u4_clkdiv2_n0010_0_cyo
    );
  H_LED_OBUF : OBUF
    port map (
      I => u1_temp_LED_2_Q,
      O => H_LED
    );
  u4_clkdiv2_n0010_1_cy : MUXCY
    port map (
      CI => u4_clkdiv2_n0010_0_cyo,
      DI => N0,
      S => u4_countd_1_rt,
      O => u4_clkdiv2_n0010_1_cyo
    );
  u4_clkdiv2_n0010_1_xor : XORCY
    port map (
      CI => u4_clkdiv2_n0010_0_cyo,
      LI => u4_countd_1_rt,
      O => u4_n0010_1_Q
    );
  u4_clkdiv2_n0010_2_cy : MUXCY
    port map (
      CI => u4_clkdiv2_n0010_1_cyo,
      DI => N0,
      S => u4_countd_2_rt,
      O => u4_clkdiv2_n0010_2_cyo
    );
  u4_clkdiv2_n0010_2_xor : XORCY
    port map (
      CI => u4_clkdiv2_n0010_1_cyo,
      LI => u4_countd_2_rt,
      O => u4_n0010_2_Q
    );
  u4_clkdiv2_n0010_3_cy : MUXCY
    port map (
      CI => u4_clkdiv2_n0010_2_cyo,
      DI => N0,
      S => u4_countd_3_rt,
      O => u4_clkdiv2_n0010_3_cyo
    );
  u4_clkdiv2_n0010_3_xor : XORCY
    port map (
      CI => u4_clkdiv2_n0010_2_cyo,
      LI => u4_countd_3_rt,
      O => u4_n0010_3_Q
    );
  u4_clkdiv2_n0010_4_cy : MUXCY
    port map (
      CI => u4_clkdiv2_n0010_3_cyo,
      DI => N0,
      S => u4_countd_4_rt,
      O => u4_clkdiv2_n0010_4_cyo
    );
  u4_clkdiv2_n0010_4_xor : XORCY
    port map (
      CI => u4_clkdiv2_n0010_3_cyo,
      LI => u4_countd_4_rt,
      O => u4_n0010_4_Q
    );
  u4_clkdiv2_counta_n0000_3_xor : XORCY
    port map (
      CI => u4_clkdiv2_counta_n0000_2_cyo,
      LI => u4_counta_3_rt,
      O => u4_counta_n0000_3_Q
    );
  u4_clkdiv2_n0009_0_lut_INV_0 : INV
    port map (
      I => u4_countc_0_Q,
      O => u4_N7
    );
  u4_clkdiv2_n0009_0_cy : MUXCY
    port map (
      CI => N0,
      DI => N1,
      S => u4_N7,
      O => u4_clkdiv2_n0009_0_cyo
    );
  M_LED_OBUF : OBUF
    port map (
      I => u1_temp_LED_1_Q,
      O => M_LED
    );
  u4_clkdiv2_n0009_1_cy : MUXCY
    port map (
      CI => u4_clkdiv2_n0009_0_cyo,
      DI => N0,
      S => u4_countc_1_rt,
      O => u4_clkdiv2_n0009_1_cyo
    );
  u4_clkdiv2_n0009_1_xor : XORCY
    port map (
      CI => u4_clkdiv2_n0009_0_cyo,
      LI => u4_countc_1_rt,
      O => u4_n0009_1_Q
    );
  u4_clkdiv2_n0009_2_cy : MUXCY
    port map (
      CI => u4_clkdiv2_n0009_1_cyo,
      DI => N0,
      S => u4_countc_2_rt,
      O => u4_clkdiv2_n0009_2_cyo
    );
  u4_clkdiv2_n0009_2_xor : XORCY
    port map (
      CI => u4_clkdiv2_n0009_1_cyo,
      LI => u4_countc_2_rt,
      O => u4_n0009_2_Q
    );
  u4_clkdiv2_n0009_3_cy : MUXCY
    port map (
      CI => u4_clkdiv2_n0009_2_cyo,
      DI => N0,
      S => u4_countc_3_rt,
      O => u4_clkdiv2_n0009_3_cyo
    );
  u4_clkdiv2_n0009_3_xor : XORCY
    port map (
      CI => u4_clkdiv2_n0009_2_cyo,
      LI => u4_countc_3_rt,
      O => u4_n0009_3_Q
    );
  u4_clkdiv2_n0009_4_cy : MUXCY
    port map (
      CI => u4_clkdiv2_n0009_3_cyo,
      DI => N0,
      S => u4_countc_4_rt,
      O => u4_clkdiv2_n0009_4_cyo
    );
  u4_clkdiv2_n0009_4_xor : XORCY
    port map (
      CI => u4_clkdiv2_n0009_3_cyo,
      LI => u4_countc_4_rt,
      O => u4_n0009_4_Q
    );
  u4_clkdiv2_counta_n0000_4_xor : XORCY
    port map (
      CI => u4_clkdiv2_counta_n0000_3_cyo,
      LI => u4_counta_4_rt,
      O => u4_counta_n0000_4_Q
    );
  u4_clkdiv2_countb_n0000_0_lut_INV_0 : INV
    port map (
      I => u4_countb_0_Q,
      O => u4_N8
    );
  u4_clkdiv2_countb_n0000_0_cy : MUXCY
    port map (
      CI => N0,
      DI => N1,
      S => u4_N8,
      O => u4_clkdiv2_countb_n0000_0_cyo
    );
  g_OBUF_31 : OBUF
    port map (
      I => g_OBUF,
      O => g
    );
  u4_clkdiv2_countb_n0000_1_cy : MUXCY
    port map (
      CI => u4_clkdiv2_countb_n0000_0_cyo,
      DI => N0,
      S => u4_countb_1_rt,
      O => u4_clkdiv2_countb_n0000_1_cyo
    );
  u4_clkdiv2_countb_n0000_1_xor : XORCY
    port map (
      CI => u4_clkdiv2_countb_n0000_0_cyo,
      LI => u4_countb_1_rt,
      O => u4_countb_n0000_1_Q
    );
  u4_clkdiv2_countb_n0000_2_cy : MUXCY
    port map (
      CI => u4_clkdiv2_countb_n0000_1_cyo,
      DI => N0,
      S => u4_countb_2_rt,
      O => u4_clkdiv2_countb_n0000_2_cyo
    );
  u4_clkdiv2_countb_n0000_2_xor : XORCY
    port map (
      CI => u4_clkdiv2_countb_n0000_1_cyo,
      LI => u4_countb_2_rt,
      O => u4_countb_n0000_2_Q
    );
  u4_clkdiv2_countb_n0000_3_cy : MUXCY
    port map (
      CI => u4_clkdiv2_countb_n0000_2_cyo,
      DI => N0,
      S => u4_countb_3_rt,
      O => u4_clkdiv2_countb_n0000_3_cyo
    );
  u4_clkdiv2_countb_n0000_3_xor : XORCY
    port map (
      CI => u4_clkdiv2_countb_n0000_2_cyo,
      LI => u4_countb_3_rt,
      O => u4_countb_n0000_3_Q
    );
  u4_clkdiv2_countb_n0000_4_cy : MUXCY
    port map (
      CI => u4_clkdiv2_countb_n0000_3_cyo,
      DI => N0,
      S => u4_countb_4_rt,
      O => u4_clkdiv2_countb_n0000_4_cyo
    );
  u4_clkdiv2_countb_n0000_4_xor : XORCY
    port map (
      CI => u4_clkdiv2_countb_n0000_3_cyo,
      LI => u4_countb_4_rt,
      O => u4_countb_n0000_4_Q
    );
  u4_clkdiv2_counta_n0000_4_cy : MUXCY
    port map (
      CI => u4_clkdiv2_counta_n0000_3_cyo,
      DI => N0,
      S => u4_counta_4_rt,
      O => u4_clkdiv2_counta_n0000_4_cyo
    );
  u4_clkdiv2_counta_n0000_0_lut_INV_0 : INV
    port map (
      I => u4_counta_0_Q,
      O => u4_N9
    );
  u4_clkdiv2_counta_n0000_0_cy : MUXCY
    port map (
      CI => N0,
      DI => N1,
      S => u4_N9,
      O => u4_clkdiv2_counta_n0000_0_cyo
    );
  L_LED_OBUF : OBUF
    port map (
      I => u1_temp_LED_0_Q,
      O => L_LED
    );
  u4_clkdiv2_counta_n0000_1_cy : MUXCY
    port map (
      CI => u4_clkdiv2_counta_n0000_0_cyo,
      DI => N0,
      S => u4_counta_1_rt,
      O => u4_clkdiv2_counta_n0000_1_cyo
    );
  u4_clkdiv2_counta_n0000_1_xor : XORCY
    port map (
      CI => u4_clkdiv2_counta_n0000_0_cyo,
      LI => u4_counta_1_rt,
      O => u4_counta_n0000_1_Q
    );
  u4_clkdiv2_counta_n0000_2_cy : MUXCY
    port map (
      CI => u4_clkdiv2_counta_n0000_1_cyo,
      DI => N0,
      S => u4_counta_2_rt,
      O => u4_clkdiv2_counta_n0000_2_cyo
    );
  u4_clkdiv2_counta_n0000_2_xor : XORCY
    port map (
      CI => u4_clkdiv2_counta_n0000_1_cyo,
      LI => u4_counta_2_rt,
      O => u4_counta_n0000_2_Q
    );
  u4_clkdiv2_counta_n0000_3_cy : MUXCY
    port map (
      CI => u4_clkdiv2_counta_n0000_2_cyo,
      DI => N0,
      S => u4_counta_3_rt,
      O => u4_clkdiv2_counta_n0000_3_cyo
    );
  u4_n00231_INV_0 : INV
    port map (
      I => u4_B,
      O => u4_n0023
    );
  Clear_IBUF_32 : IBUF
    port map (
      I => Clear,
      O => Clear_IBUF
    );
  u4_n0007_0_2 : LUT4
    generic map(
      INIT => X"0100"
    )
    port map (
      I0 => u4_countc_0_Q,
      I1 => u4_countb_0_Q,
      I2 => u4_N33,
      I3 => u4_countb_1_Q,
      O => u4_n0007_0_Q
    );
  Start_IBUF_33 : IBUF
    port map (
      I => Start,
      O => Start_IBUF
    );
  u4_n0008_1_2 : LUT4_L
    generic map(
      INIT => X"0020"
    )
    port map (
      I0 => u4_n0010_1_Q,
      I1 => u4_countc_0_Q,
      I2 => u4_countc_1_Q,
      I3 => u4_N19,
      LO => u4_n0008_1_Q
    );
  key9_IBUF_34 : IBUF
    port map (
      I => key9,
      O => key9_IBUF
    );
  u4_n0008_2_2 : LUT4_L
    generic map(
      INIT => X"0020"
    )
    port map (
      I0 => u4_n0010_2_Q,
      I1 => u4_countc_0_Q,
      I2 => u4_countc_1_Q,
      I3 => u4_N19,
      LO => u4_n0008_2_Q
    );
  key8_IBUF_35 : IBUF
    port map (
      I => key8,
      O => key8_IBUF
    );
  u4_n0008_3_2 : LUT4_L
    generic map(
      INIT => X"0020"
    )
    port map (
      I0 => u4_n0010_3_Q,
      I1 => u4_countc_0_Q,
      I2 => u4_countc_1_Q,
      I3 => u4_N19,
      LO => u4_n0008_3_Q
    );
  u1_temp_LED_2 : FDSE
    port map (
      D => u1_n0005_2_Q,
      S => u1_n0004,
      CE => u1_temp_LED_N0,
      C => u6_B,
      Q => u1_temp_LED_2_Q
    );
  u1_Counter_Reset_36 : FDR
    port map (
      D => N1,
      R => u1_n0017,
      C => u6_B,
      Q => u1_Counter_Reset
    );
  u1_n0004_37 : LUT4
    generic map(
      INIT => X"D555"
    )
    port map (
      I0 => Clear_IBUF,
      I1 => u3_COUNT_0_Q,
      I2 => u3_COUNT_1_Q,
      I3 => N5,
      O => u1_n0004
    );
  u1_n00171 : LUT4
    generic map(
      INIT => X"4CCC"
    )
    port map (
      I0 => u3_COUNT_2_Q,
      I1 => Clear_IBUF,
      I2 => u3_COUNT_1_Q,
      I3 => N232,
      O => u1_n0017
    );
  u1_n00161 : LUT2
    generic map(
      INIT => X"D"
    )
    port map (
      I0 => Start_IBUF,
      I1 => u1_n0004,
      O => u1_n0016
    );
  u1_n00171_SW0 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => u3_COUNT_0_Q,
      I1 => u3_COUNT_3_Q,
      O => N232
    );
  u1_n0005_2_1 : LUT4
    generic map(
      INIT => X"AB8E"
    )
    port map (
      I0 => u1_temp_LED_2_Q,
      I1 => key8_IBUF,
      I2 => key9_IBUF,
      I3 => key7_IBUF,
      O => u1_n0005_2_Q
    );
  u1_temp_LED_0 : FDSE
    port map (
      D => u1_n0005_0_Q,
      S => u1_n0004,
      CE => u1_temp_LED_N0,
      C => u6_B,
      Q => u1_temp_LED_0_Q
    );
  u1_temp_LED_1 : FDSE
    port map (
      D => u1_n0005_1_Q,
      S => u1_n0004,
      CE => u1_temp_LED_N0,
      C => u6_B,
      Q => u1_temp_LED_1_Q
    );
  u1_n0005_1_1 : LUT4
    generic map(
      INIT => X"AB8E"
    )
    port map (
      I0 => u1_temp_LED_1_Q,
      I1 => key7_IBUF,
      I2 => key8_IBUF,
      I3 => key9_IBUF,
      O => u1_n0005_1_Q
    );
  u1_EN_38 : FDCE
    generic map(
      INIT => '0'
    )
    port map (
      D => u1_n0002,
      CE => u1_n0016,
      CLR => u1_EN_N0,
      C => u6_B,
      Q => u1_EN
    );
  u1_n0005_0_1 : LUT4
    generic map(
      INIT => X"AB8E"
    )
    port map (
      I0 => u1_temp_LED_0_Q,
      I1 => key8_IBUF,
      I2 => key7_IBUF,
      I3 => key9_IBUF,
      O => u1_n0005_0_Q
    );
  u1_EN_Aclr_INV1_INV_0 : INV
    port map (
      I => Door_IBUF,
      O => u1_EN_N0
    );
  u1_temp_LED_ClkEn_INV1_INV_0 : INV
    port map (
      I => Set_IBUF,
      O => u1_temp_LED_N0
    );
  u2_Qn_1 : FDE
    port map (
      D => u2_n0002_1_Q,
      CE => Set_IBUF,
      C => u4_B,
      Q => u2_Qn_1_Q
    );
  u2_kload_39 : FDE
    port map (
      D => N198,
      CE => Set_IBUF,
      C => u4_B,
      Q => u2_kload