microoven_synthesis.vhd

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      CI => u6_clkdiv3_n0009_0_cyo,
      LI => u6_countc_1_rt,
      O => u6_n0009_1_Q
    );
  u6_clkdiv3_n0009_2_cy : MUXCY
    port map (
      CI => u6_clkdiv3_n0009_1_cyo,
      DI => N0,
      S => u6_countc_2_rt,
      O => u6_clkdiv3_n0009_2_cyo
    );
  u6_clkdiv3_n0009_2_xor : XORCY
    port map (
      CI => u6_clkdiv3_n0009_1_cyo,
      LI => u6_countc_2_rt,
      O => u6_n0009_2_Q
    );
  u6_clkdiv3_n0009_3_cy : MUXCY
    port map (
      CI => u6_clkdiv3_n0009_2_cyo,
      DI => N0,
      S => u6_countc_3_rt,
      O => u6_clkdiv3_n0009_3_cyo
    );
  u6_clkdiv3_n0009_3_xor : XORCY
    port map (
      CI => u6_clkdiv3_n0009_2_cyo,
      LI => u6_countc_3_rt,
      O => u6_n0009_3_Q
    );
  u6_clkdiv3_counta_n0000_3_xor : XORCY
    port map (
      CI => u6_clkdiv3_counta_n0000_2_cyo,
      LI => u6_counta_3_rt,
      O => u6_counta_n0000_3_Q
    );
  u6_clkdiv3_countb_n0000_0_lut_INV_0 : INV
    port map (
      I => u6_countb_0_Q,
      O => u6_N8
    );
  u6_clkdiv3_countb_n0000_0_cy : MUXCY
    port map (
      CI => N0,
      DI => N1,
      S => u6_N8,
      O => u6_clkdiv3_countb_n0000_0_cyo
    );
  c_OBUF_15 : OBUF
    port map (
      I => c_OBUF,
      O => c
    );
  u6_clkdiv3_countb_n0000_1_cy : MUXCY
    port map (
      CI => u6_clkdiv3_countb_n0000_0_cyo,
      DI => N0,
      S => u6_countb_1_rt,
      O => u6_clkdiv3_countb_n0000_1_cyo
    );
  u6_clkdiv3_countb_n0000_1_xor : XORCY
    port map (
      CI => u6_clkdiv3_countb_n0000_0_cyo,
      LI => u6_countb_1_rt,
      O => u6_countb_n0000_1_Q
    );
  u6_clkdiv3_countb_n0000_2_cy : MUXCY
    port map (
      CI => u6_clkdiv3_countb_n0000_1_cyo,
      DI => N0,
      S => u6_countb_2_rt,
      O => u6_clkdiv3_countb_n0000_2_cyo
    );
  u6_clkdiv3_countb_n0000_2_xor : XORCY
    port map (
      CI => u6_clkdiv3_countb_n0000_1_cyo,
      LI => u6_countb_2_rt,
      O => u6_countb_n0000_2_Q
    );
  u6_clkdiv3_countb_n0000_3_cy : MUXCY
    port map (
      CI => u6_clkdiv3_countb_n0000_2_cyo,
      DI => N0,
      S => u6_countb_3_rt,
      O => u6_clkdiv3_countb_n0000_3_cyo
    );
  u6_clkdiv3_countb_n0000_3_xor : XORCY
    port map (
      CI => u6_clkdiv3_countb_n0000_2_cyo,
      LI => u6_countb_3_rt,
      O => u6_countb_n0000_3_Q
    );
  u6_clkdiv3_counta_n0000_3_cy : MUXCY
    port map (
      CI => u6_clkdiv3_counta_n0000_2_cyo,
      DI => N0,
      S => u6_counta_3_rt,
      O => u6_clkdiv3_counta_n0000_3_cyo
    );
  u6_clkdiv3_counta_n0000_0_lut_INV_0 : INV
    port map (
      I => u6_counta_0_Q,
      O => u6_N9
    );
  u6_clkdiv3_counta_n0000_0_cy : MUXCY
    port map (
      CI => N0,
      DI => N1,
      S => u6_N9,
      O => u6_clkdiv3_counta_n0000_0_cyo
    );
  d_OBUF_16 : OBUF
    port map (
      I => d_OBUF,
      O => d
    );
  u6_clkdiv3_counta_n0000_1_cy : MUXCY
    port map (
      CI => u6_clkdiv3_counta_n0000_0_cyo,
      DI => N0,
      S => u6_counta_1_rt,
      O => u6_clkdiv3_counta_n0000_1_cyo
    );
  u6_clkdiv3_counta_n0000_1_xor : XORCY
    port map (
      CI => u6_clkdiv3_counta_n0000_0_cyo,
      LI => u6_counta_1_rt,
      O => u6_counta_n0000_1_Q
    );
  u6_clkdiv3_counta_n0000_2_cy : MUXCY
    port map (
      CI => u6_clkdiv3_counta_n0000_1_cyo,
      DI => N0,
      S => u6_counta_2_rt,
      O => u6_clkdiv3_counta_n0000_2_cyo
    );
  u6_n00231_INV_0 : INV
    port map (
      I => u6_B,
      O => u6_n0023
    );
  b_OBUF_17 : OBUF
    port map (
      I => b_OBUF,
      O => b
    );
  u6_n0007_0_2 : LUT3
    generic map(
      INIT => X"01"
    )
    port map (
      I0 => u6_countc_0_Q,
      I1 => u6_countb_0_Q,
      I2 => u6_N29,
      O => u6_n0007_0_Q
    );
  a_OBUF_18 : OBUF
    port map (
      I => a_OBUF,
      O => a
    );
  u6_n0008_1_2 : LUT3_L
    generic map(
      INIT => X"02"
    )
    port map (
      I0 => u6_n0010_1_Q,
      I1 => u6_countc_0_Q,
      I2 => u6_N17,
      LO => u6_n0008_1_Q
    );
  Set_IBUF_19 : IBUF
    port map (
      I => Set,
      O => Set_IBUF
    );
  u6_n0008_2_2 : LUT3_L
    generic map(
      INIT => X"02"
    )
    port map (
      I0 => u6_n0010_2_Q,
      I1 => u6_countc_0_Q,
      I2 => u6_N17,
      LO => u6_n0008_2_Q
    );
  u4_clkdiv2_n0010_5_xor : XORCY
    port map (
      CI => u4_clkdiv2_n0010_4_cyo,
      LI => u4_countd_5_rt,
      O => u4_n0010_5_Q
    );
  u4_n00251 : LUT4
    generic map(
      INIT => X"0302"
    )
    port map (
      I0 => u4_n0012,
      I1 => u4_n0005,
      I2 => u4_n0011,
      I3 => N240,
      O => u4_n0025
    );
  u4_n00241 : LUT3
    generic map(
      INIT => X"32"
    )
    port map (
      I0 => u4_n0011,
      I1 => u4_n0005,
      I2 => u4_n0012,
      O => u4_n0024
    );
  u4_n0007_2_2 : LUT4_L
    generic map(
      INIT => X"0020"
    )
    port map (
      I0 => u4_n0009_2_Q,
      I1 => u4_countb_0_Q,
      I2 => u4_countb_1_Q,
      I3 => u4_N33,
      LO => u4_n0007_2_Q
    );
  u4_n00221 : LUT4
    generic map(
      INIT => X"0100"
    )
    port map (
      I0 => u4_n0005,
      I1 => u4_n0011,
      I2 => u4_n0012,
      I3 => u4_n0021,
      O => u4_n0022
    );
  u4_n0021_20 : LUT4_D
    generic map(
      INIT => X"0100"
    )
    port map (
      I0 => u4_countd_0_Q,
      I1 => u4_countd_2_Q,
      I2 => N220,
      I3 => u4_countd_1_Q,
      LO => N240,
      O => u4_n0021
    );
  u4_countd_2 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      D => u4_n0008_2_Q,
      CE => u4_n0025,
      C => Clk_BUFGP,
      Q => u4_countd_2_Q
    );
  u4_countd_4 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      D => u4_n0008_4_Q,
      CE => u4_n0025,
      C => Clk_BUFGP,
      Q => u4_countd_4_Q
    );
  u4_countd_1 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      D => u4_n0008_1_Q,
      CE => u4_n0025,
      C => Clk_BUFGP,
      Q => u4_countd_1_Q
    );
  u4_countd_3 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      D => u4_n0008_3_Q,
      CE => u4_n0025,
      C => Clk_BUFGP,
      Q => u4_countd_3_Q
    );
  u4_countd_0 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      D => u4_n0008_0_Q,
      CE => u4_n0025,
      C => Clk_BUFGP,
      Q => u4_countd_0_Q
    );
  u4_n0012_21 : LUT4
    generic map(
      INIT => X"0100"
    )
    port map (
      I0 => u4_countc_0_Q,
      I1 => u4_countc_2_Q,
      I2 => N222,
      I3 => u4_countc_1_Q,
      O => u4_n0012
    );
  u4_n0011_22 : LUT4
    generic map(
      INIT => X"0100"
    )
    port map (
      I0 => u4_countb_0_Q,
      I1 => u4_countb_2_Q,
      I2 => N224,
      I3 => u4_countb_1_Q,
      O => u4_n0011
    );
  u4_n0007_2_1 : LUT4
    generic map(
      INIT => X"FFBF"
    )
    port map (
      I0 => u4_countb_2_Q,
      I1 => u4_countb_4_Q,
      I2 => u4_countb_5_Q,
      I3 => u4_countb_3_Q,
      O => u4_N33
    );
  u4_n0007_3_2 : LUT4_L
    generic map(
      INIT => X"0020"
    )
    port map (
      I0 => u4_n0009_3_Q,
      I1 => u4_countb_0_Q,
      I2 => u4_countb_1_Q,
      I3 => u4_N33,
      LO => u4_n0007_3_Q
    );
  u4_countc_5_rt_23 : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => u4_countc_5_Q,
      O => u4_countc_5_rt
    );
  u4_n0007_4_2 : LUT4_L
    generic map(
      INIT => X"0020"
    )
    port map (
      I0 => u4_n0009_4_Q,
      I1 => u4_countb_0_Q,
      I2 => u4_countb_1_Q,
      I3 => u4_N33,
      LO => u4_n0007_4_Q
    );
  Clk_BUFGP_24 : BUFGP
    port map (
      I => Clk,
      O => Clk_BUFGP
    );
  u4_n0007_5_2 : LUT4_L
    generic map(
      INIT => X"0020"
    )
    port map (
      I0 => u4_n0009_5_Q,
      I1 => u4_countb_0_Q,
      I2 => u4_countb_1_Q,
      I3 => u4_N33,
      LO => u4_n0007_5_Q
    );
  key0_IBUF_25 : IBUF
    port map (
      I => key0,
      O => key0_IBUF
    );
  u4_n0007_1_2 : LUT4_L
    generic map(
      INIT => X"0020"
    )
    port map (
      I0 => u4_n0009_1_Q,
      I1 => u4_countb_0_Q,
      I2 => u4_countb_1_Q,
      I3 => u4_N33,
      LO => u4_n0007_1_Q
    );
  u4_B_26 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      D => u4_n0023,
      CE => u4_n0022,
      C => Clk_BUFGP,
      Q => u4_B
    );
  u4_counta_4 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      D => u4_counta_n0000_4_Q,
      R => u4_n0005,
      C => Clk_BUFGP,
      Q => u4_counta_4_Q
    );
  u4_countb_4 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      D => u4_countb_n0000_4_Q,
      R => u4_n0006,
      CE => u4_n0005,
      C => Clk_BUFGP,
      Q => u4_countb_4_Q
    );
  u4_countc_5 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      D => u4_n0007_5_Q,
      CE => u4_n0024,
      C => Clk_BUFGP,
      Q => u4_countc_5_Q
    );
  u4_countd_5 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      D => u4_n0008_5_Q,
      CE => u4_n0025,
      C => Clk_BUFGP,
      Q => u4_countd_5_Q
    );
  u4_clkdiv2_n0009_5_xor : XORCY
    port map (
      CI => u4_clkdiv2_n0009_4_cyo,
      LI => u4_countc_5_rt,
      O => u4_n0009_5_Q
    );
  u4_n0005_27 : LUT4
    generic map(
      INIT => X"0100"
    )
    port map (
      I0 => u4_counta_0_Q,
      I1 => u4_counta_2_Q,
      I2 => N226,
      I3 => u4_counta_1_Q,
      O => u4_n0005
    );
  u4_n00061 : LUT2
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => u4_n0011,
      I1 => u4_n0005,
      O => u4_n0006
    );
  key1_IBUF_28 : IBUF
    port map (
      I => key1,
      O => key1_IBUF
    );
  u6_n0008_0_2 : LUT3
    generic map(
      INIT => X"01"
    )
    port map (
      I0 => u6_countd_0_Q,
      I1 => u6_countc_0_Q,
      I2 => u6_N17,
      O => u6_n0008_0_Q
    );
  key2_IBUF_29 : IBUF
    port map (
      I => key2,
      O => key2_IBUF
    );
  u4_n0008_5_2 : LUT4_L
    generic map(
      INIT => X"0020"
    )
    port map (
      I0 => u4_n0010_5_Q,
      I1 => u4_countc_0_Q,
      I2 => u4_countc_1_Q,
      I3 => u4_N19,
      LO => u4_n0008_5_Q
    );
  u4_countc_0 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      D => u4_n0007_0_Q,
      CE => u4_n0024,
      C => Clk_BUFGP,
      Q => u4_countc_0_Q
    );
  u4_countc_1 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      D => u4_n0007_1_Q,
      CE => u4_n0024,
      C => Clk_BUFGP,
      Q => u4_countc_1_Q
    );
  u4_countc_2 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      D => u4_n0007_2_Q,
      CE => u4_n0024,
      C => Clk_BUFGP,
      Q => u4_countc_2_Q
    );
  u4_countc_3 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      D => u4_n0007_3_Q,
      CE => u4_n0024,
      C => Clk_BUFGP,
      Q => u4_countc_3_Q
    );
  u4_countc_4 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      D => u4_n0007_4_Q,
      CE => u4_n0024,
      C => Clk_BUFGP,
      Q => u4_countc_4_Q
    );
  u4_countb_5 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      D => u4_countb_n0000_5_Q,
      R => u4_n0006,
      CE => u4_n0005,
      C => Clk_BUFGP,
      Q => u4_countb_5_Q
    );
  u4_clkdiv2_countb_n0000_5_xor : XORCY
    port map (
      CI => u4_clkdiv2_countb_n0000_4_cyo,
      LI => u4_countb_5_rt,
      O => u4_countb_n0000_5_Q
    );
  u4_countb_0 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      D => u4_N8,
      R => u4_n0006,
      CE => u4_n0005,
      C => Clk_BUFGP,
      Q => u4_countb_0_Q
    );
  u4_countb_1 : FDRE
    generic map(
      INIT => '0'
    )
    port map (