microoven_synthesis.vhd

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    generic map(
      INIT => X"8"
    )
    port map (
      I0 => u2_Qn_3_Q,
      I1 => u2_kload,
      O => u3_COUNT_0_3_n0001
    );
  u3_COUNT_1_n00001 : LUT3
    generic map(
      INIT => X"F4"
    )
    port map (
      I0 => u2_Qn_1_Q,
      I1 => u2_kload,
      I2 => u1_Counter_Reset,
      O => u3_COUNT_0_1_n0000
    );
  u3_COUNT_0_n00001 : LUT3
    generic map(
      INIT => X"F4"
    )
    port map (
      I0 => u2_Qn_0_Q,
      I1 => u2_kload,
      I2 => u1_Counter_Reset,
      O => u3_COUNT_0_0_n0000
    );
  u3_COUNT_3 : FDCPE
    port map (
      D => u3_COUNT_n0001_3_Q,
      CE => u1_EN,
      CLR => u3_COUNT_0_3_n0000,
      PRE => u3_COUNT_0_3_n0001,
      C => u4_B,
      Q => u3_COUNT_3_Q
    );
  u3_COUNT_2_n00001 : LUT3
    generic map(
      INIT => X"F4"
    )
    port map (
      I0 => u2_Qn_2_Q,
      I1 => u2_kload,
      I2 => u1_Counter_Reset,
      O => u3_COUNT_0_2_n0000
    );
  u3_COUNT_2 : FDCPE
    port map (
      D => u3_COUNT_n0001_2_Q,
      CE => u1_EN,
      CLR => u3_COUNT_0_2_n0000,
      PRE => u3_COUNT_0_2_n0001,
      C => u4_B,
      Q => u3_COUNT_2_Q
    );
  u3_COUNT_3_n00001 : LUT3
    generic map(
      INIT => X"F4"
    )
    port map (
      I0 => u2_Qn_3_Q,
      I1 => u2_kload,
      I2 => u1_Counter_Reset,
      O => u3_COUNT_0_3_n0000
    );
  u6_clkdiv3_n0010_4_xor : XORCY
    port map (
      CI => u6_clkdiv3_n0010_3_cyo,
      LI => u6_countd_4_rt,
      O => u6_n0010_4_Q
    );
  u6_n00251 : LUT4
    generic map(
      INIT => X"0302"
    )
    port map (
      I0 => N239,
      I1 => u6_n0005,
      I2 => u6_n0011,
      I3 => u6_n0021,
      O => u6_n0025
    );
  u6_n00241 : LUT3
    generic map(
      INIT => X"32"
    )
    port map (
      I0 => u6_n0011,
      I1 => u6_n0005,
      I2 => u6_n0012,
      O => u6_n0024
    );
  u6_n0007_3_2 : LUT3_L
    generic map(
      INIT => X"02"
    )
    port map (
      I0 => u6_n0009_3_Q,
      I1 => u6_countb_0_Q,
      I2 => u6_N29,
      LO => u6_n0007_3_Q
    );
  u6_n00221 : LUT4
    generic map(
      INIT => X"0100"
    )
    port map (
      I0 => u6_n0005,
      I1 => u6_n0011,
      I2 => u6_n0012,
      I3 => u6_n0021,
      O => u6_n0022
    );
  u6_n0021_2 : LUT4
    generic map(
      INIT => X"0020"
    )
    port map (
      I0 => N212,
      I1 => u6_countd_0_Q,
      I2 => u6_countd_2_Q,
      I3 => u6_countd_1_Q,
      O => u6_n0021
    );
  u6_countd_1 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      D => u6_n0008_1_Q,
      CE => u6_n0025,
      C => Clk_BUFGP,
      Q => u6_countd_1_Q
    );
  u6_countd_3 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      D => u6_n0008_3_Q,
      CE => u6_n0025,
      C => Clk_BUFGP,
      Q => u6_countd_3_Q
    );
  u6_countd_0 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      D => u6_n0008_0_Q,
      CE => u6_n0025,
      C => Clk_BUFGP,
      Q => u6_countd_0_Q
    );
  u6_countd_2 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      D => u6_n0008_2_Q,
      CE => u6_n0025,
      C => Clk_BUFGP,
      Q => u6_countd_2_Q
    );
  u6_countc_3 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      D => u6_n0007_3_Q,
      CE => u6_n0024,
      C => Clk_BUFGP,
      Q => u6_countc_3_Q
    );
  u6_n0012_3 : LUT4_D
    generic map(
      INIT => X"0020"
    )
    port map (
      I0 => N214,
      I1 => u6_countc_0_Q,
      I2 => u6_countc_2_Q,
      I3 => u6_countc_1_Q,
      LO => N239,
      O => u6_n0012
    );
  u6_n0011_4 : LUT4
    generic map(
      INIT => X"0020"
    )
    port map (
      I0 => N216,
      I1 => u6_countb_0_Q,
      I2 => u6_countb_2_Q,
      I3 => u6_countb_1_Q,
      O => u6_n0011
    );
  u6_n0007_3_1 : LUT4
    generic map(
      INIT => X"FF7F"
    )
    port map (
      I0 => u6_countb_2_Q,
      I1 => u6_countb_3_Q,
      I2 => u6_countb_4_Q,
      I3 => u6_countb_1_Q,
      O => u6_N29
    );
  u6_n0007_4_2 : LUT3_L
    generic map(
      INIT => X"02"
    )
    port map (
      I0 => u6_n0009_4_Q,
      I1 => u6_countb_0_Q,
      I2 => u6_N29,
      LO => u6_n0007_4_Q
    );
  key3_IBUF_5 : IBUF
    port map (
      I => key3,
      O => key3_IBUF
    );
  u6_n0007_2_2 : LUT3_L
    generic map(
      INIT => X"02"
    )
    port map (
      I0 => u6_n0009_2_Q,
      I1 => u6_countb_0_Q,
      I2 => u6_N29,
      LO => u6_n0007_2_Q
    );
  key4_IBUF_6 : IBUF
    port map (
      I => key4,
      O => key4_IBUF
    );
  u6_n0007_1_2 : LUT3_L
    generic map(
      INIT => X"02"
    )
    port map (
      I0 => u6_n0009_1_Q,
      I1 => u6_countb_0_Q,
      I2 => u6_N29,
      LO => u6_n0007_1_Q
    );
  key5_IBUF_7 : IBUF
    port map (
      I => key5,
      O => key5_IBUF
    );
  u4_countb_5_rt_8 : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => u4_countb_5_Q,
      O => u4_countb_5_rt
    );
  u6_B_9 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      D => u6_n0023,
      CE => u6_n0022,
      C => Clk_BUFGP,
      Q => u6_B
    );
  u6_counta_3 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      D => u6_counta_n0000_3_Q,
      R => u6_n0005,
      C => Clk_BUFGP,
      Q => u6_counta_3_Q
    );
  u6_countb_3 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      D => u6_countb_n0000_3_Q,
      R => u6_n0006,
      CE => u6_n0005,
      C => Clk_BUFGP,
      Q => u6_countb_3_Q
    );
  u6_countc_4 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      D => u6_n0007_4_Q,
      CE => u6_n0024,
      C => Clk_BUFGP,
      Q => u6_countc_4_Q
    );
  u6_countd_4 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      D => u6_n0008_4_Q,
      CE => u6_n0025,
      C => Clk_BUFGP,
      Q => u6_countd_4_Q
    );
  u6_clkdiv3_n0009_4_xor : XORCY
    port map (
      CI => u6_clkdiv3_n0009_3_cyo,
      LI => u6_countc_4_rt,
      O => u6_n0009_4_Q
    );
  u6_n0005_10 : LUT4
    generic map(
      INIT => X"0020"
    )
    port map (
      I0 => N218,
      I1 => u6_counta_0_Q,
      I2 => u6_counta_2_Q,
      I3 => u6_counta_1_Q,
      O => u6_n0005
    );
  u6_n00061 : LUT2
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => u6_n0011,
      I1 => u6_n0005,
      O => u6_n0006
    );
  key6_IBUF_11 : IBUF
    port map (
      I => key6,
      O => key6_IBUF
    );
  u6_n0008_4_2 : LUT3_L
    generic map(
      INIT => X"02"
    )
    port map (
      I0 => u6_n0010_4_Q,
      I1 => u6_countc_0_Q,
      I2 => u6_N17,
      LO => u6_n0008_4_Q
    );
  u6_countc_0 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      D => u6_n0007_0_Q,
      CE => u6_n0024,
      C => Clk_BUFGP,
      Q => u6_countc_0_Q
    );
  u6_countc_1 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      D => u6_n0007_1_Q,
      CE => u6_n0024,
      C => Clk_BUFGP,
      Q => u6_countc_1_Q
    );
  u6_countc_2 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      D => u6_n0007_2_Q,
      CE => u6_n0024,
      C => Clk_BUFGP,
      Q => u6_countc_2_Q
    );
  u6_countb_4 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      D => u6_countb_n0000_4_Q,
      R => u6_n0006,
      CE => u6_n0005,
      C => Clk_BUFGP,
      Q => u6_countb_4_Q
    );
  u6_clkdiv3_countb_n0000_4_xor : XORCY
    port map (
      CI => u6_clkdiv3_countb_n0000_3_cyo,
      LI => u6_countb_4_rt,
      O => u6_countb_n0000_4_Q
    );
  u6_countb_0 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      D => u6_N8,
      R => u6_n0006,
      CE => u6_n0005,
      C => Clk_BUFGP,
      Q => u6_countb_0_Q
    );
  u6_countb_1 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      D => u6_countb_n0000_1_Q,
      R => u6_n0006,
      CE => u6_n0005,
      C => Clk_BUFGP,
      Q => u6_countb_1_Q
    );
  u6_countb_2 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      D => u6_countb_n0000_2_Q,
      R => u6_n0006,
      CE => u6_n0005,
      C => Clk_BUFGP,
      Q => u6_countb_2_Q
    );
  u6_counta_4 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      D => u6_counta_n0000_4_Q,
      R => u6_n0005,
      C => Clk_BUFGP,
      Q => u6_counta_4_Q
    );
  u6_clkdiv3_counta_n0000_4_xor : XORCY
    port map (
      CI => u6_clkdiv3_counta_n0000_3_cyo,
      LI => u6_counta_4_rt,
      O => u6_counta_n0000_4_Q
    );
  u6_counta_0 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      D => u6_N9,
      R => u6_n0005,
      C => Clk_BUFGP,
      Q => u6_counta_0_Q
    );
  u6_counta_1 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      D => u6_counta_n0000_1_Q,
      R => u6_n0005,
      C => Clk_BUFGP,
      Q => u6_counta_1_Q
    );
  u6_counta_2 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      D => u6_counta_n0000_2_Q,
      R => u6_n0005,
      C => Clk_BUFGP,
      Q => u6_counta_2_Q
    );
  Door_IBUF_12 : IBUF
    port map (
      I => Door,
      O => Door_IBUF
    );
  u6_n0008_3_2 : LUT3_L
    generic map(
      INIT => X"02"
    )
    port map (
      I0 => u6_n0010_3_Q,
      I1 => u6_countc_0_Q,
      I2 => u6_N17,
      LO => u6_n0008_3_Q
    );
  u6_clkdiv3_n0010_0_lut_INV_0 : INV
    port map (
      I => u6_countd_0_Q,
      O => u6_N6
    );
  u6_clkdiv3_n0010_0_cy : MUXCY
    port map (
      CI => N0,
      DI => N1,
      S => u6_N6,
      O => u6_clkdiv3_n0010_0_cyo
    );
  e_OBUF_13 : OBUF
    port map (
      I => e_OBUF,
      O => e
    );
  u6_clkdiv3_n0010_1_cy : MUXCY
    port map (
      CI => u6_clkdiv3_n0010_0_cyo,
      DI => N0,
      S => u6_countd_1_rt,
      O => u6_clkdiv3_n0010_1_cyo
    );
  u6_clkdiv3_n0010_1_xor : XORCY
    port map (
      CI => u6_clkdiv3_n0010_0_cyo,
      LI => u6_countd_1_rt,
      O => u6_n0010_1_Q
    );
  u6_clkdiv3_n0010_2_cy : MUXCY
    port map (
      CI => u6_clkdiv3_n0010_1_cyo,
      DI => N0,
      S => u6_countd_2_rt,
      O => u6_clkdiv3_n0010_2_cyo
    );
  u6_clkdiv3_n0010_2_xor : XORCY
    port map (
      CI => u6_clkdiv3_n0010_1_cyo,
      LI => u6_countd_2_rt,
      O => u6_n0010_2_Q
    );
  u6_clkdiv3_n0010_3_cy : MUXCY
    port map (
      CI => u6_clkdiv3_n0010_2_cyo,
      DI => N0,
      S => u6_countd_3_rt,
      O => u6_clkdiv3_n0010_3_cyo
    );
  u6_clkdiv3_n0010_3_xor : XORCY
    port map (
      CI => u6_clkdiv3_n0010_2_cyo,
      LI => u6_countd_3_rt,
      O => u6_n0010_3_Q
    );
  u6_clkdiv3_counta_n0000_2_xor : XORCY
    port map (
      CI => u6_clkdiv3_counta_n0000_1_cyo,
      LI => u6_counta_2_rt,
      O => u6_counta_n0000_2_Q
    );
  u6_clkdiv3_n0009_0_lut_INV_0 : INV
    port map (
      I => u6_countc_0_Q,
      O => u6_N7
    );
  u6_clkdiv3_n0009_0_cy : MUXCY
    port map (
      CI => N0,
      DI => N1,
      S => u6_N7,
      O => u6_clkdiv3_n0009_0_cyo
    );
  f_OBUF_14 : OBUF
    port map (
      I => f_OBUF,
      O => f
    );
  u6_clkdiv3_n0009_1_cy : MUXCY
    port map (
      CI => u6_clkdiv3_n0009_0_cyo,
      DI => N0,
      S => u6_countc_1_rt,
      O => u6_clkdiv3_n0009_1_cyo
    );
  u6_clkdiv3_n0009_1_xor : XORCY
    port map (