microoven_synthesis.vhd

微波爐．．．．．．．．．．．．．．．．．．．．．．．．．．

--------------------------------------------------------------------------------
-- Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.
--------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor: Xilinx
-- \   \   \/     Version: H.42
--  \   \         Application: netgen
--  /   /         Filename: microoven_synthesis.vhd
-- /___/   /\     Timestamp: Fri Mar 13 15:28:02 2009
-- \   \  /  \ 
--  \___\/\___\
--             
-- Command	: -intstyle ise -ar Structure -w -ofmt vhdl -sim microoven.ngc microoven_synthesis.vhd 
-- Device	: xc2s50e-6-tq144
-- Input file	: microoven.ngc
-- Output file	: microoven_synthesis.vhd
-- # of Entities	: 1
-- Design Name	: microoven
-- Xilinx	: c:/xilinx
--             
-- Purpose:    
--     This VHDL netlist is a verification model and uses simulation 
--     primitives which may not represent the true implementation of the 
--     device, however the netlist is functionally correct and should not 
--     be modified. This file cannot be synthesized and should only be used 
--     with supported simulation tools.
--             
-- Reference:  
--     Development System Reference Guide, Chapter 23
--     Synthesis and Verification Design Guide, Chapter 6
--             
--------------------------------------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;

entity microoven is
  port (
    Clk : in STD_LOGIC := 'X'; 
    key0 : in STD_LOGIC := 'X'; 
    key1 : in STD_LOGIC := 'X'; 
    key2 : in STD_LOGIC := 'X'; 
    key3 : in STD_LOGIC := 'X'; 
    key4 : in STD_LOGIC := 'X'; 
    key5 : in STD_LOGIC := 'X'; 
    key6 : in STD_LOGIC := 'X'; 
    key7 : in STD_LOGIC := 'X'; 
    key8 : in STD_LOGIC := 'X'; 
    key9 : in STD_LOGIC := 'X'; 
    Start : in STD_LOGIC := 'X'; 
    Clear : in STD_LOGIC := 'X'; 
    Door : in STD_LOGIC := 'X'; 
    Set : in STD_LOGIC := 'X'; 
    a : out STD_LOGIC; 
    b : out STD_LOGIC; 
    c : out STD_LOGIC; 
    d : out STD_LOGIC; 
    e : out STD_LOGIC; 
    f : out STD_LOGIC; 
    g : out STD_LOGIC; 
    L_LED : out STD_LOGIC; 
    H_LED : out STD_LOGIC; 
    M_LED : out STD_LOGIC 
  );
end microoven;

architecture Structure of microoven is
  signal Clk_BUFGP : STD_LOGIC; 
  signal key0_IBUF : STD_LOGIC; 
  signal key1_IBUF : STD_LOGIC; 
  signal key2_IBUF : STD_LOGIC; 
  signal key3_IBUF : STD_LOGIC; 
  signal key4_IBUF : STD_LOGIC; 
  signal key5_IBUF : STD_LOGIC; 
  signal key6_IBUF : STD_LOGIC; 
  signal key7_IBUF : STD_LOGIC; 
  signal key8_IBUF : STD_LOGIC; 
  signal key9_IBUF : STD_LOGIC; 
  signal Start_IBUF : STD_LOGIC; 
  signal Clear_IBUF : STD_LOGIC; 
  signal a_OBUF : STD_LOGIC; 
  signal b_OBUF : STD_LOGIC; 
  signal c_OBUF : STD_LOGIC; 
  signal d_OBUF : STD_LOGIC; 
  signal e_OBUF : STD_LOGIC; 
  signal f_OBUF : STD_LOGIC; 
  signal g_OBUF : STD_LOGIC; 
  signal u1_temp_LED_0_Q : STD_LOGIC; 
  signal u1_temp_LED_2_Q : STD_LOGIC; 
  signal Door_IBUF : STD_LOGIC; 
  signal u1_temp_LED_1_Q : STD_LOGIC; 
  signal Set_IBUF : STD_LOGIC; 
  signal u4_B : STD_LOGIC; 
  signal u2_Qn_0_Q : STD_LOGIC; 
  signal u1_Counter_Reset : STD_LOGIC; 
  signal u1_EN : STD_LOGIC; 
  signal u6_B : STD_LOGIC; 
  signal N0 : STD_LOGIC; 
  signal u2_Qn_1_Q : STD_LOGIC; 
  signal u2_Qn_3_Q : STD_LOGIC; 
  signal u2_Qn_2_Q : STD_LOGIC; 
  signal u3_COUNT_3_Q : STD_LOGIC; 
  signal u2_kload : STD_LOGIC; 
  signal u3_COUNT_1_Q : STD_LOGIC; 
  signal u3_COUNT_2_Q : STD_LOGIC; 
  signal u3_COUNT_0_Q : STD_LOGIC; 
  signal N1 : STD_LOGIC; 
  signal u3_COUNT_0_1_n0000 : STD_LOGIC; 
  signal u3_COUNT_0_3_n0000 : STD_LOGIC; 
  signal u3_COUNT_n0001_3_Q : STD_LOGIC; 
  signal u3_COUNT_n0001_2_Q : STD_LOGIC; 
  signal u3_COUNT_0_0_n0001 : STD_LOGIC; 
  signal u3_COUNT_0_3_n0001 : STD_LOGIC; 
  signal u3_COUNT_n0001_0_Q : STD_LOGIC; 
  signal u3_COUNT_0_2_n0000 : STD_LOGIC; 
  signal u3_COUNT_n0001_1_Q : STD_LOGIC; 
  signal u3_COUNT_0_1_n0001 : STD_LOGIC; 
  signal u3_COUNT_0_2_n0001 : STD_LOGIC; 
  signal u3_COUNT_0_0_n0000 : STD_LOGIC; 
  signal u6_N29 : STD_LOGIC; 
  signal u6_countc_1_Q : STD_LOGIC; 
  signal u6_n0005 : STD_LOGIC; 
  signal u6_n0011 : STD_LOGIC; 
  signal u6_n0006 : STD_LOGIC; 
  signal u6_n0012 : STD_LOGIC; 
  signal u6_countc_3_Q : STD_LOGIC; 
  signal u6_countc_4_Q : STD_LOGIC; 
  signal u6_countc_2_Q : STD_LOGIC; 
  signal u6_n0007_3_Q : STD_LOGIC; 
  signal u6_countb_0_Q : STD_LOGIC; 
  signal u6_n0021 : STD_LOGIC; 
  signal u6_n0010_2_Q : STD_LOGIC; 
  signal u6_counta_1_Q : STD_LOGIC; 
  signal u6_n0022 : STD_LOGIC; 
  signal u6_n0009_4_Q : STD_LOGIC; 
  signal u6_n0008_2_Q : STD_LOGIC; 
  signal u6_n0023 : STD_LOGIC; 
  signal u6_n0010_1_Q : STD_LOGIC; 
  signal u6_countc_0_Q : STD_LOGIC; 
  signal u6_n0024 : STD_LOGIC; 
  signal u6_n0009_3_Q : STD_LOGIC; 
  signal u6_countb_1_Q : STD_LOGIC; 
  signal u6_n0025 : STD_LOGIC; 
  signal u6_n0008_1_Q : STD_LOGIC; 
  signal u6_counta_0_Q : STD_LOGIC; 
  signal u6_n0008_0_Q : STD_LOGIC; 
  signal u6_countb_4_Q : STD_LOGIC; 
  signal u6_counta_4_Q : STD_LOGIC; 
  signal u6_countb_3_Q : STD_LOGIC; 
  signal u6_counta_3_Q : STD_LOGIC; 
  signal u6_countb_2_Q : STD_LOGIC; 
  signal u6_n0008_3_Q : STD_LOGIC; 
  signal u6_counta_2_Q : STD_LOGIC; 
  signal u6_n0009_2_Q : STD_LOGIC; 
  signal u6_n0007_2_Q : STD_LOGIC; 
  signal u6_n0009_1_Q : STD_LOGIC; 
  signal u6_n0007_1_Q : STD_LOGIC; 
  signal u6_n0007_0_Q : STD_LOGIC; 
  signal u6_n0007_4_Q : STD_LOGIC; 
  signal u6_n0008_4_Q : STD_LOGIC; 
  signal u6_countd_4_Q : STD_LOGIC; 
  signal u6_countd_3_Q : STD_LOGIC; 
  signal u6_countd_2_Q : STD_LOGIC; 
  signal u6_countd_1_Q : STD_LOGIC; 
  signal u6_countd_0_Q : STD_LOGIC; 
  signal u6_n0010_4_Q : STD_LOGIC; 
  signal u6_n0010_3_Q : STD_LOGIC; 
  signal u6_countb_n0000_2_Q : STD_LOGIC; 
  signal u6_countb_n0000_3_Q : STD_LOGIC; 
  signal u6_countb_n0000_4_Q : STD_LOGIC; 
  signal u6_countb_n0000_1_Q : STD_LOGIC; 
  signal u6_counta_n0000_2_Q : STD_LOGIC; 
  signal u6_counta_n0000_3_Q : STD_LOGIC; 
  signal u6_counta_n0000_1_Q : STD_LOGIC; 
  signal u6_counta_n0000_4_Q : STD_LOGIC; 
  signal u6_clkdiv3_countb_n0000_3_cyo : STD_LOGIC; 
  signal u6_clkdiv3_counta_n0000_3_cyo : STD_LOGIC; 
  signal u6_clkdiv3_counta_n0000_2_cyo : STD_LOGIC; 
  signal u6_clkdiv3_counta_n0000_1_cyo : STD_LOGIC; 
  signal u6_N6 : STD_LOGIC; 
  signal u6_clkdiv3_n0010_0_cyo : STD_LOGIC; 
  signal u6_clkdiv3_n0010_1_cyo : STD_LOGIC; 
  signal u6_clkdiv3_n0010_2_cyo : STD_LOGIC; 
  signal u6_clkdiv3_n0010_3_cyo : STD_LOGIC; 
  signal u6_clkdiv3_counta_n0000_0_cyo : STD_LOGIC; 
  signal u6_N7 : STD_LOGIC; 
  signal u6_clkdiv3_n0009_0_cyo : STD_LOGIC; 
  signal u6_clkdiv3_n0009_1_cyo : STD_LOGIC; 
  signal u6_clkdiv3_n0009_2_cyo : STD_LOGIC; 
  signal u6_clkdiv3_n0009_3_cyo : STD_LOGIC; 
  signal u6_N9 : STD_LOGIC; 
  signal u6_N8 : STD_LOGIC; 
  signal u6_clkdiv3_countb_n0000_0_cyo : STD_LOGIC; 
  signal u6_clkdiv3_countb_n0000_1_cyo : STD_LOGIC; 
  signal u6_clkdiv3_countb_n0000_2_cyo : STD_LOGIC; 
  signal u6_N17 : STD_LOGIC; 
  signal u4_N33 : STD_LOGIC; 
  signal N218 : STD_LOGIC; 
  signal u4_countc_1_Q : STD_LOGIC; 
  signal u4_n0005 : STD_LOGIC; 
  signal u4_n0011 : STD_LOGIC; 
  signal u4_n0006 : STD_LOGIC; 
  signal u4_n0012 : STD_LOGIC; 
  signal u4_countc_3_Q : STD_LOGIC; 
  signal u4_countc_4_Q : STD_LOGIC; 
  signal u4_countc_2_Q : STD_LOGIC; 
  signal u4_n0009_4_Q : STD_LOGIC; 
  signal u4_n0007_2_Q : STD_LOGIC; 
  signal u4_countc_5_Q : STD_LOGIC; 
  signal u4_n0021 : STD_LOGIC; 
  signal u4_counta_0_Q : STD_LOGIC; 
  signal u4_n0022 : STD_LOGIC; 
  signal u4_n0009_3_Q : STD_LOGIC; 
  signal u4_n0008_1_Q : STD_LOGIC; 
  signal u4_n0023 : STD_LOGIC; 
  signal u4_n0009_5_Q : STD_LOGIC; 
  signal u4_countc_0_Q : STD_LOGIC; 
  signal u4_n0024 : STD_LOGIC; 
  signal u4_n0009_2_Q : STD_LOGIC; 
  signal u4_countb_1_Q : STD_LOGIC; 
  signal u4_n0025 : STD_LOGIC; 
  signal u4_countb_0_Q : STD_LOGIC; 
  signal u4_countb_5_Q : STD_LOGIC; 
  signal u4_n0008_0_Q : STD_LOGIC; 
  signal u4_countb_4_Q : STD_LOGIC; 
  signal u4_counta_5_Q : STD_LOGIC; 
  signal u4_countb_3_Q : STD_LOGIC; 
  signal u4_counta_4_Q : STD_LOGIC; 
  signal u4_countb_2_Q : STD_LOGIC; 
  signal u4_n0008_5_Q : STD_LOGIC; 
  signal u4_counta_3_Q : STD_LOGIC; 
  signal u4_n0008_4_Q : STD_LOGIC; 
  signal u4_counta_2_Q : STD_LOGIC; 
  signal u4_n0008_3_Q : STD_LOGIC; 
  signal u4_counta_1_Q : STD_LOGIC; 
  signal u4_n0008_2_Q : STD_LOGIC; 
  signal u4_n0007_1_Q : STD_LOGIC; 
  signal u4_n0009_1_Q : STD_LOGIC; 
  signal u4_n0007_0_Q : STD_LOGIC; 
  signal u4_n0007_5_Q : STD_LOGIC; 
  signal u4_n0007_4_Q : STD_LOGIC; 
  signal u4_n0007_3_Q : STD_LOGIC; 
  signal u4_countd_5_Q : STD_LOGIC; 
  signal u4_countd_4_Q : STD_LOGIC; 
  signal u4_countd_3_Q : STD_LOGIC; 
  signal u4_countd_2_Q : STD_LOGIC; 
  signal u4_countd_1_Q : STD_LOGIC; 
  signal u4_countd_0_Q : STD_LOGIC; 
  signal u4_n0010_5_Q : STD_LOGIC; 
  signal u4_n0010_4_Q : STD_LOGIC; 
  signal u4_n0010_3_Q : STD_LOGIC; 
  signal u4_n0010_2_Q : STD_LOGIC; 
  signal u4_n0010_1_Q : STD_LOGIC; 
  signal u4_countb_n0000_2_Q : STD_LOGIC; 
  signal u4_countb_n0000_3_Q : STD_LOGIC; 
  signal u4_countb_n0000_4_Q : STD_LOGIC; 
  signal u4_countb_n0000_1_Q : STD_LOGIC; 
  signal u4_countb_n0000_5_Q : STD_LOGIC; 
  signal u4_counta_n0000_2_Q : STD_LOGIC; 
  signal u4_counta_n0000_3_Q : STD_LOGIC; 
  signal u4_counta_n0000_1_Q : STD_LOGIC; 
  signal u4_counta_n0000_4_Q : STD_LOGIC; 
  signal u4_counta_n0000_5_Q : STD_LOGIC; 
  signal u4_N9 : STD_LOGIC; 
  signal u4_clkdiv2_counta_n0000_4_cyo : STD_LOGIC; 
  signal u4_clkdiv2_counta_n0000_3_cyo : STD_LOGIC; 
  signal u4_clkdiv2_counta_n0000_2_cyo : STD_LOGIC; 
  signal u4_N6 : STD_LOGIC; 
  signal u4_clkdiv2_n0010_0_cyo : STD_LOGIC; 
  signal u4_clkdiv2_n0010_1_cyo : STD_LOGIC; 
  signal u4_clkdiv2_n0010_2_cyo : STD_LOGIC; 
  signal u4_clkdiv2_n0010_3_cyo : STD_LOGIC; 
  signal u4_clkdiv2_n0010_4_cyo : STD_LOGIC; 
  signal u4_clkdiv2_counta_n0000_1_cyo : STD_LOGIC; 
  signal u4_N7 : STD_LOGIC; 
  signal u4_clkdiv2_n0009_0_cyo : STD_LOGIC; 
  signal u4_clkdiv2_n0009_1_cyo : STD_LOGIC; 
  signal u4_clkdiv2_n0009_2_cyo : STD_LOGIC; 
  signal u4_clkdiv2_n0009_3_cyo : STD_LOGIC; 
  signal u4_clkdiv2_n0009_4_cyo : STD_LOGIC; 
  signal u4_clkdiv2_counta_n0000_0_cyo : STD_LOGIC; 
  signal u4_N8 : STD_LOGIC; 
  signal u4_clkdiv2_countb_n0000_0_cyo : STD_LOGIC; 
  signal u4_clkdiv2_countb_n0000_1_cyo : STD_LOGIC; 
  signal u4_clkdiv2_countb_n0000_2_cyo : STD_LOGIC; 
  signal u4_clkdiv2_countb_n0000_3_cyo : STD_LOGIC; 
  signal u4_clkdiv2_countb_n0000_4_cyo : STD_LOGIC; 
  signal u4_N19 : STD_LOGIC; 
  signal u1_temp_LED_N0 : STD_LOGIC; 
  signal u1_n0016 : STD_LOGIC; 
  signal u1_n0017 : STD_LOGIC; 
  signal u1_EN_N0 : STD_LOGIC; 
  signal N232 : STD_LOGIC; 
  signal u1_n0005_1_Q : STD_LOGIC; 
  signal u1_n0005_2_Q : STD_LOGIC; 
  signal u1_n0002 : STD_LOGIC; 
  signal u1_n0004 : STD_LOGIC; 
  signal u1_n0005_0_Q : STD_LOGIC; 
  signal u2_N14 : STD_LOGIC; 
  signal u2_n0002_1_Q : STD_LOGIC; 
  signal u2_N15 : STD_LOGIC; 
  signal N220 : STD_LOGIC; 
  signal u2_N16 : STD_LOGIC; 
  signal u2_n0002_2_Q : STD_LOGIC; 
  signal N230 : STD_LOGIC; 
  signal u2_n0002_3_Q : STD_LOGIC; 
  signal N5 : STD_LOGIC; 
  signal N7 : STD_LOGIC; 
  signal N9 : STD_LOGIC; 
  signal N214 : STD_LOGIC; 
  signal N212 : STD_LOGIC; 
  signal u4_countd_5_rt : STD_LOGIC; 
  signal N198 : STD_LOGIC; 
  signal N226 : STD_LOGIC; 
  signal CHOICE693 : STD_LOGIC; 
  signal CHOICE704 : STD_LOGIC; 
  signal N222 : STD_LOGIC; 
  signal CHOICE675 : STD_LOGIC; 
  signal CHOICE708 : STD_LOGIC; 
  signal u4_countb_5_rt : STD_LOGIC; 
  signal N228 : STD_LOGIC; 
  signal CHOICE705 : STD_LOGIC; 
  signal u4_countc_5_rt : STD_LOGIC; 
  signal N104 : STD_LOGIC; 
  signal N216 : STD_LOGIC; 
  signal u4_counta_5_rt : STD_LOGIC; 
  signal N224 : STD_LOGIC; 
  signal u6_countd_1_rt : STD_LOGIC; 
  signal u6_countd_2_rt : STD_LOGIC; 
  signal u6_countd_3_rt : STD_LOGIC; 
  signal u6_countc_1_rt : STD_LOGIC; 
  signal u6_countc_2_rt : STD_LOGIC; 
  signal u6_countc_3_rt : STD_LOGIC; 
  signal u6_countb_1_rt : STD_LOGIC; 
  signal u6_countb_2_rt : STD_LOGIC; 
  signal u6_countb_3_rt : STD_LOGIC; 
  signal u6_counta_3_rt : STD_LOGIC; 
  signal u6_counta_1_rt : STD_LOGIC; 
  signal u6_counta_2_rt : STD_LOGIC; 
  signal u4_countd_1_rt : STD_LOGIC; 
  signal u4_countd_2_rt : STD_LOGIC; 
  signal u4_countd_3_rt : STD_LOGIC; 
  signal u4_countd_4_rt : STD_LOGIC; 
  signal u4_countc_1_rt : STD_LOGIC; 
  signal u4_countc_2_rt : STD_LOGIC; 
  signal u4_countc_3_rt : STD_LOGIC; 
  signal u4_countc_4_rt : STD_LOGIC; 
  signal u4_countb_1_rt : STD_LOGIC; 
  signal u4_countb_2_rt : STD_LOGIC; 
  signal u4_countb_3_rt : STD_LOGIC; 
  signal u4_countb_4_rt : STD_LOGIC; 
  signal u4_counta_4_rt : STD_LOGIC; 
  signal u4_counta_1_rt : STD_LOGIC; 
  signal u4_counta_2_rt : STD_LOGIC; 
  signal u4_counta_3_rt : STD_LOGIC; 
  signal u6_countd_4_rt : STD_LOGIC; 
  signal u6_countc_4_rt : STD_LOGIC; 
  signal u6_countb_4_rt : STD_LOGIC; 
  signal u6_counta_4_rt : STD_LOGIC; 
  signal N237 : STD_LOGIC; 
  signal N238 : STD_LOGIC; 
  signal N239 : STD_LOGIC; 
  signal N240 : STD_LOGIC; 
begin
  XST_GND : GND
    port map (
      G => N0
    );
  u5_Mrom_output_inst_lut4_61 : LUT4
    generic map(
      INIT => X"2812"
    )
    port map (
      I0 => u3_COUNT_0_Q,
      I1 => u3_COUNT_1_Q,
      I2 => u3_COUNT_2_Q,
      I3 => u3_COUNT_3_Q,
      O => g_OBUF
    );
  u6_n0008_3_1 : LUT4
    generic map(
      INIT => X"FF7F"
    )
    port map (
      I0 => u6_countc_2_Q,
      I1 => u6_countc_3_Q,
      I2 => u6_countc_4_Q,
      I3 => u6_countc_1_Q,
      O => u6_N17
    );
  u4_n0008_4_1 : LUT4
    generic map(
      INIT => X"FFBF"
    )
    port map (
      I0 => u4_countc_2_Q,
      I1 => u4_countc_4_Q,
      I2 => u4_countc_5_Q,
      I3 => u4_countc_3_Q,
      O => u4_N19
    );
  u3_COUNT_1 : FDCPE
    port map (
      D => u3_COUNT_n0001_1_Q,
      CE => u1_EN,
      CLR => u3_COUNT_0_1_n0000,
      PRE => u3_COUNT_0_1_n0001,
      C => u4_B,
      Q => u3_COUNT_1_Q
    );
  u2_Ker151 : LUT4
    generic map(
      INIT => X"0001"
    )
    port map (
      I0 => key8_IBUF,
      I1 => key9_IBUF,
      I2 => key0_IBUF,
      I3 => key1_IBUF,
      O => u2_N15
    );
  u1_n00021 : LUT2
    generic map(
      INIT => X"1"
    )
    port map (
      I0 => u1_n0004,
      I1 => u1_EN,
      O => u1_n0002
    );
  XST_VCC : VCC
    port map (
      P => N1
    );
  u5_Mrom_output_inst_lut4_01 : LUT4
    generic map(
      INIT => X"1083"
    )
    port map (
      I0 => u3_COUNT_0_Q,
      I1 => u3_COUNT_1_Q,
      I2 => u3_COUNT_2_Q,
      I3 => u3_COUNT_3_Q,
      O => a_OBUF
    );
  u5_Mrom_output_inst_lut4_11 : LUT4
    generic map(
      INIT => X"6032"
    )
    port map (
      I0 => u3_COUNT_1_Q,
      I1 => u3_COUNT_3_Q,
      I2 => u3_COUNT_0_Q,
      I3 => u3_COUNT_2_Q,
      O => b_OBUF
    );
  u5_Mrom_output_inst_lut4_21 : LUT4
    generic map(
      INIT => X"10F4"
    )
    port map (
      I0 => u3_COUNT_1_Q,
      I1 => u3_COUNT_2_Q,
      I2 => u3_COUNT_0_Q,
      I3 => u3_COUNT_3_Q,
      O => c_OBUF
    );
  u5_Mrom_output_inst_lut4_31 : LUT4
    generic map(
      INIT => X"8492"
    )
    port map (
      I0 => u3_COUNT_0_Q,
      I1 => u3_COUNT_1_Q,
      I2 => u3_COUNT_2_Q,
      I3 => u3_COUNT_3_Q,
      O => d_OBUF
    );
  u5_Mrom_output_inst_lut4_41 : LUT4
    generic map(
      INIT => X"8098"
    )
    port map (
      I0 => u3_COUNT_2_Q,
      I1 => u3_COUNT_3_Q,
      I2 => u3_COUNT_1_Q,
      I3 => u3_COUNT_0_Q,
      O => e_OBUF
    );
  u5_Mrom_output_inst_lut4_51 : LUT4
    generic map(
      INIT => X"D680"
    )
    port map (
      I0 => u3_COUNT_0_Q,
      I1 => u3_COUNT_1_Q,
      I2 => u3_COUNT_3_Q,
      I3 => u3_COUNT_2_Q,
      O => f_OBUF
    );
  u3_COUNT_0 : FDCPE
    port map (
      D => u3_COUNT_n0001_0_Q,
      CE => u1_EN,
      CLR => u3_COUNT_0_0_n0000,
      PRE => u3_COUNT_0_0_n0001,
      C => u4_B,
      Q => u3_COUNT_0_Q
    );
  u3_COUNT_n0001_0_1 : LUT3
    generic map(
      INIT => X"B1"
    )
    port map (
      I0 => u2_kload,
      I1 => u3_COUNT_0_Q,
      I2 => u2_Qn_0_Q,
      O => u3_COUNT_n0001_0_Q
    );
  u3_COUNT_1_n00011 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => u2_Qn_1_Q,
      I1 => u2_kload,
      O => u3_COUNT_0_1_n0001
    );
  u3_COUNT_n0001_3_Q_0 : LUT4_L
    generic map(
      INIT => X"EB41"
    )
    port map (
      I0 => u2_kload,
      I1 => N230,
      I2 => u3_COUNT_3_Q,
      I3 => u2_Qn_3_Q,
      LO => u3_COUNT_n0001_3_Q
    );
  u3_COUNT_0_n00011 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => u2_Qn_0_Q,
      I1 => u2_kload,
      O => u3_COUNT_0_0_n0001
    );
  u3_COUNT_n0001_2_Q_1 : LUT4_L
    generic map(
      INIT => X"EB41"
    )
    port map (
      I0 => u2_kload,
      I1 => N228,
      I2 => u3_COUNT_2_Q,
      I3 => u2_Qn_2_Q,
      LO => u3_COUNT_n0001_2_Q
    );
  u3_COUNT_n0001_1_1 : LUT4
    generic map(
      INIT => X"EB41"
    )
    port map (
      I0 => u2_kload,
      I1 => u3_COUNT_0_Q,
      I2 => u3_COUNT_1_Q,
      I3 => u2_Qn_1_Q,
      O => u3_COUNT_n0001_1_Q
    );
  u3_COUNT_2_n00011 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => u2_Qn_2_Q,
      I1 => u2_kload,
      O => u3_COUNT_0_2_n0001
    );
  u3_COUNT_3_n00011 : LUT2