counter.tbw

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version 3
d:\ksc\my_project\lab2\counter.vhd
counter
VHDL
VHDL
counter.xwv
Clocked
-
-
1000000000
ns
GSR:false
PRLD:false
100000000
CLOCK_LIST_BEGIN
CLK
50000000
50000000
10000000
10000000
0
RISING
CLOCK_LIST_END
SIGNAL_LIST_BEGIN
CE
CLK
COUNT
CLK
DIN
CLK
DIR
CLK
LOAD
CLK
RESET
CLK
TC
CLK
SIGNAL_LIST_END
SIGNALS_NOT_ON_DISPLAY
TC_DIFF
SIGNALS_NOT_ON_DISPLAY_END
MARKER_LIST_BEGIN
MARKER_LIST_END
MEASURE_LIST_BEGIN
MEASURE_LIST_END
SIGNAL_ORDER_BEGIN
CLK
CE
DIR
LOAD
RESET
DIN
TC
COUNT
SIGNAL_ORDER_END
-X-X-X-