key_number_encoder_timesim.vhd

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--------------------------------------------------------------------------------
-- Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.
--------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor: Xilinx
-- \   \   \/     Version: H.42
--  \   \         Application: netgen
--  /   /         Filename: key_number_encoder_timesim.vhd
-- /___/   /\     Timestamp: Tue Mar 10 15:32:23 2009
-- \   \  /  \ 
--  \___\/\___\
--             
-- Command	: -intstyle ise -s 6 -pcf key_number_encoder.pcf -rpw 100 -tpw 0 -ar Structure -xon true -w -ofmt vhdl -sim key_number_encoder.ncd key_number_encoder_timesim.vhd 
-- Device	: 2s50etq144-6 (PRODUCTION 1.18 2005-01-22)
-- Input file	: key_number_encoder.ncd
-- Output file	: key_number_encoder_timesim.vhd
-- # of Entities	: 1
-- Design Name	: key_number_encoder
-- Xilinx	: c:/xilinx
--             
-- Purpose:    
--     This VHDL netlist is a verification model and uses simulation 
--     primitives which may not represent the true implementation of the 
--     device, however the netlist is functionally correct and should not 
--     be modified. This file cannot be synthesized and should only be used 
--     with supported simulation tools.
--             
-- Reference:  
--     Development System Reference Guide, Chapter 23
--     Synthesis and Verification Design Guide, Chapter 6
--             
--------------------------------------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library SIMPRIM;
use SIMPRIM.VCOMPONENTS.ALL;
use SIMPRIM.VPACKAGE.ALL;

entity key_number_encoder is
  port (
    clk : in STD_LOGIC := 'X'; 
    key_en : in STD_LOGIC := 'X'; 
    kload : out STD_LOGIC; 
    key_in : in STD_LOGIC_VECTOR ( 9 downto 0 ); 
    Qn : out STD_LOGIC_VECTOR ( 3 downto 0 ) 
  );
end key_number_encoder;

architecture Structure of key_number_encoder is
  signal key_in_0_IBUF_0 : STD_LOGIC; 
  signal key_in_1_IBUF_0 : STD_LOGIC; 
  signal key_in_2_IBUF_0 : STD_LOGIC; 
  signal key_in_3_IBUF_0 : STD_LOGIC; 
  signal key_en_IBUF_0 : STD_LOGIC; 
  signal key_in_4_IBUF_0 : STD_LOGIC; 
  signal key_in_5_IBUF_0 : STD_LOGIC; 
  signal key_in_6_IBUF_0 : STD_LOGIC; 
  signal key_in_7_IBUF_0 : STD_LOGIC; 
  signal key_in_8_IBUF_0 : STD_LOGIC; 
  signal key_in_9_IBUF_0 : STD_LOGIC; 
  signal clk_BUFGP : STD_LOGIC; 
  signal N120_0 : STD_LOGIC; 
  signal CHOICE254_0 : STD_LOGIC; 
  signal CHOICE284_0 : STD_LOGIC; 
  signal CHOICE272_0 : STD_LOGIC; 
  signal N16_0 : STD_LOGIC; 
  signal CHOICE287 : STD_LOGIC; 
  signal N14 : STD_LOGIC; 
  signal N15_0 : STD_LOGIC; 
  signal CHOICE283 : STD_LOGIC; 
  signal N23 : STD_LOGIC; 
  signal N25 : STD_LOGIC; 
  signal GSR : STD_LOGIC; 
  signal GTS : STD_LOGIC; 
  signal key_in_0_IBUF : STD_LOGIC; 
  signal key_in_1_IBUF : STD_LOGIC; 
  signal key_in_2_IBUF : STD_LOGIC; 
  signal key_in_3_IBUF : STD_LOGIC; 
  signal key_en_IBUF : STD_LOGIC; 
  signal key_in_4_IBUF : STD_LOGIC; 
  signal key_in_5_IBUF : STD_LOGIC; 
  signal key_in_6_IBUF : STD_LOGIC; 
  signal key_in_7_IBUF : STD_LOGIC; 
  signal key_in_8_IBUF : STD_LOGIC; 
  signal key_in_9_IBUF : STD_LOGIC; 
  signal Qn_0_ENABLE : STD_LOGIC; 
  signal Qn_0_OUTMUX : STD_LOGIC; 
  signal Qn_0 : STD_LOGIC; 
  signal Qn_0_OD : STD_LOGIC; 
  signal Qn_0_OFF_RST : STD_LOGIC; 
  signal Qn_1_ENABLE : STD_LOGIC; 
  signal Qn_1_OUTMUX : STD_LOGIC; 
  signal Qn_1 : STD_LOGIC; 
  signal Qn_1_OD : STD_LOGIC; 
  signal Qn_1_OFF_RST : STD_LOGIC; 
  signal Qn_2_ENABLE : STD_LOGIC; 
  signal Qn_2_OUTMUX : STD_LOGIC; 
  signal Qn_2 : STD_LOGIC; 
  signal Qn_2_OD : STD_LOGIC; 
  signal Qn_2_OFF_RST : STD_LOGIC; 
  signal Qn_3_ENABLE : STD_LOGIC; 
  signal Qn_3_OUTMUX : STD_LOGIC; 
  signal Qn_3 : STD_LOGIC; 
  signal Qn_3_OD : STD_LOGIC; 
  signal Qn_3_OFF_RST : STD_LOGIC; 
  signal kload_ENABLE : STD_LOGIC; 
  signal kload_OUTMUX : STD_LOGIC; 
  signal kload_OBUF : STD_LOGIC; 
  signal kload_OD : STD_LOGIC; 
  signal kload_OFF_RST : STD_LOGIC; 
  signal N223 : STD_LOGIC; 
  signal N222 : STD_LOGIC; 
  signal CHOICE254 : STD_LOGIC; 
  signal CHOICE287_pack_1 : STD_LOGIC; 
  signal N214 : STD_LOGIC; 
  signal N14_pack_1 : STD_LOGIC; 
  signal N120 : STD_LOGIC; 
  signal N15 : STD_LOGIC; 
  signal N16 : STD_LOGIC; 
  signal CHOICE272 : STD_LOGIC; 
  signal CHOICE283_pack_1 : STD_LOGIC; 
  signal CHOICE284 : STD_LOGIC; 
  signal N23_pack_1 : STD_LOGIC; 
  signal N25_pack_1 : STD_LOGIC; 
  signal GND : STD_LOGIC; 
  signal VCC : STD_LOGIC; 
  signal Q_n0002 : STD_LOGIC_VECTOR ( 3 downto 1 ); 
begin
  key_in_0_IMUX : X_BUF
    port map (
      I => key_in_0_IBUF,
      O => key_in_0_IBUF_0
    );
  key_in_0_IBUF_1 : X_BUF
    port map (
      I => key_in(0),
      O => key_in_0_IBUF
    );
  key_in_1_IMUX : X_BUF
    port map (
      I => key_in_1_IBUF,
      O => key_in_1_IBUF_0
    );
  key_in_1_IBUF_2 : X_BUF
    port map (
      I => key_in(1),
      O => key_in_1_IBUF
    );
  key_in_2_IMUX : X_BUF
    port map (
      I => key_in_2_IBUF,
      O => key_in_2_IBUF_0
    );
  key_in_2_IBUF_3 : X_BUF
    port map (
      I => key_in(2),
      O => key_in_2_IBUF
    );
  key_in_3_IMUX : X_BUF
    port map (
      I => key_in_3_IBUF,
      O => key_in_3_IBUF_0
    );
  key_in_3_IBUF_4 : X_BUF
    port map (
      I => key_in(3),
      O => key_in_3_IBUF
    );
  key_en_IMUX : X_BUF
    port map (
      I => key_en_IBUF,
      O => key_en_IBUF_0
    );
  key_en_IBUF_5 : X_BUF
    port map (
      I => key_en,
      O => key_en_IBUF
    );
  key_in_4_IMUX : X_BUF
    port map (
      I => key_in_4_IBUF,
      O => key_in_4_IBUF_0
    );
  key_in_4_IBUF_6 : X_BUF
    port map (
      I => key_in(4),
      O => key_in_4_IBUF
    );
  key_in_5_IMUX : X_BUF
    port map (
      I => key_in_5_IBUF,
      O => key_in_5_IBUF_0
    );
  key_in_5_IBUF_7 : X_BUF
    port map (
      I => key_in(5),
      O => key_in_5_IBUF
    );
  key_in_6_IMUX : X_BUF
    port map (
      I => key_in_6_IBUF,
      O => key_in_6_IBUF_0
    );
  key_in_6_IBUF_8 : X_BUF
    port map (
      I => key_in(6),
      O => key_in_6_IBUF
    );
  key_in_7_IMUX : X_BUF
    port map (
      I => key_in_7_IBUF,
      O => key_in_7_IBUF_0
    );
  key_in_7_IBUF_9 : X_BUF
    port map (
      I => key_in(7),
      O => key_in_7_IBUF
    );
  key_in_8_IMUX : X_BUF
    port map (
      I => key_in_8_IBUF,
      O => key_in_8_IBUF_0
    );
  key_in_8_IBUF_10 : X_BUF
    port map (
      I => key_in(8),
      O => key_in_8_IBUF
    );
  key_in_9_IMUX : X_BUF
    port map (
      I => key_in_9_IBUF,
      O => key_in_9_IBUF_0
    );
  key_in_9_IBUF_11 : X_BUF
    port map (
      I => key_in(9),
      O => key_in_9_IBUF
    );
  Qn_0_OBUF : X_TRI
    port map (
      I => Qn_0_OUTMUX,
      CTL => Qn_0_ENABLE,
      O => Qn(0)
    );
  Qn_0_ENABLEINV : X_INV
    port map (
      I => GTS,
      O => Qn_0_ENABLE
    );
  Qn_0_OUTMUX_12 : X_BUF
    port map (
      I => Qn_0,
      O => Qn_0_OUTMUX
    );
  Qn_0_OMUX : X_BUF
    port map (
      I => N120_0,
      O => Qn_0_OD
    );
  Qn_0_13 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Qn_0_OD,
      CE => key_en_IBUF_0,
      CLK => clk_BUFGP,
      SET => GND,
      RST => Qn_0_OFF_RST,
      O => Qn_0
    );
  Qn_0_OFF_RSTOR : X_BUF
    port map (
      I => GSR,
      O => Qn_0_OFF_RST
    );
  Qn_1_OBUF : X_TRI
    port map (
      I => Qn_1_OUTMUX,
      CTL => Qn_1_ENABLE,
      O => Qn(1)
    );
  Qn_1_ENABLEINV : X_INV
    port map (
      I => GTS,
      O => Qn_1_ENABLE
    );
  Qn_1_OUTMUX_14 : X_BUF
    port map (
      I => Qn_1,
      O => Qn_1_OUTMUX
    );
  Qn_1_OMUX : X_BUF
    port map (
      I => Q_n0002(1),
      O => Qn_1_OD
    );
  Qn_1_15 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Qn_1_OD,
      CE => key_en_IBUF_0,
      CLK => clk_BUFGP,
      SET => GND,
      RST => Qn_1_OFF_RST,
      O => Qn_1
    );
  Qn_1_OFF_RSTOR : X_BUF
    port map (
      I => GSR,
      O => Qn_1_OFF_RST
    );
  Qn_2_OBUF : X_TRI
    port map (
      I => Qn_2_OUTMUX,
      CTL => Qn_2_ENABLE,
      O => Qn(2)
    );
  Qn_2_ENABLEINV : X_INV
    port map (
      I => GTS,
      O => Qn_2_ENABLE
    );
  Qn_2_OUTMUX_16 : X_BUF
    port map (
      I => Qn_2,
      O => Qn_2_OUTMUX
    );
  Qn_2_OMUX : X_BUF
    port map (
      I => Q_n0002(2),
      O => Qn_2_OD
    );
  Qn_2_17 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Qn_2_OD,
      CE => key_en_IBUF_0,
      CLK => clk_BUFGP,
      SET => GND,
      RST => Qn_2_OFF_RST,
      O => Qn_2
    );
  Qn_2_OFF_RSTOR : X_BUF
    port map (
      I => GSR,
      O => Qn_2_OFF_RST
    );
  Qn_3_OBUF : X_TRI
    port map (
      I => Qn_3_OUTMUX,
      CTL => Qn_3_ENABLE,
      O => Qn(3)
    );
  Qn_3_ENABLEINV : X_INV
    port map (
      I => GTS,
      O => Qn_3_ENABLE
    );
  Qn_3_OUTMUX_18 : X_BUF
    port map (
      I => Qn_3,
      O => Qn_3_OUTMUX
    );
  Qn_3_OMUX : X_BUF
    port map (
      I => Q_n0002(3),
      O => Qn_3_OD
    );
  Qn_3_19 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Qn_3_OD,
      CE => key_en_IBUF_0,
      CLK => clk_BUFGP,
      SET => GND,
      RST => Qn_3_OFF_RST,
      O => Qn_3
    );
  Qn_3_OFF_RSTOR : X_BUF
    port map (
      I => GSR,
      O => Qn_3_OFF_RST
    );
  kload_OBUF_20 : X_TRI
    port map (
      I => kload_OUTMUX,
      CTL => kload_ENABLE,
      O => kload
    );
  kload_ENABLEINV : X_INV
    port map (
      I => GTS,
      O => kload_ENABLE
    );
  kload_OUTMUX_21 : X_BUF
    port map (
      I => kload_OBUF,
      O => kload_OUTMUX
    );
  kload_OMUX : X_BUF
    port map (
      I => N214,
      O => kload_OD
    );
  kload_22 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => kload_OD,
      CE => key_en_IBUF_0,
      CLK => clk_BUFGP,
      SET => GND,
      RST => kload_OFF_RST,
      O => kload_OBUF
    );
  kload_OFF_RSTOR : X_BUF
    port map (
      I => GSR,
      O => kload_OFF_RST
    );
  Q_n0002_0_125 : X_MUX2
    port map (
      IA => N222,
      IB => N223,
      SEL => key_in_9_IBUF_0,
      O => CHOICE254
    );
  Q_n0002_0_125_G : X_LUT4
    generic map(
      INIT => X"0001"
    )
    port map (
      ADR0 => key_in_5_IBUF_0,
      ADR1 => key_in_3_IBUF_0,
      ADR2 => key_in_7_IBUF_0,
      ADR3 => key_in_1_IBUF_0,
      O => N223
    );
  Q_n0002_0_125_F : X_LUT4
    generic map(
      INIT => X"0116"
    )
    port map (
      ADR0 => key_in_7_IBUF_0,
      ADR1 => key_in_5_IBUF_0,
      ADR2 => key_in_1_IBUF_0,
      ADR3 => key_in_3_IBUF_0,
      O => N222
    );
  CHOICE254_XUSED : X_BUF
    port map (
      I => CHOICE254,
      O => CHOICE254_0
    );
  Q_n0005127 : X_LUT4
    generic map(
      INIT => X"0A0E"
    )
    port map (
      ADR0 => CHOICE284_0,
      ADR1 => CHOICE272_0,
      ADR2 => key_in_9_IBUF_0,
      ADR3 => key_in_4_IBUF_0,
      O => CHOICE287_pack_1
    );
  Q_n0005161 : X_LUT4
    generic map(
      INIT => X"FCF0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => N16_0,
      ADR2 => N120_0,
      ADR3 => CHOICE287,
      O => N214
    );
  CHOICE287_XUSED : X_BUF
    port map (
      I => CHOICE287_pack_1,
      O => CHOICE287
    );
  Ker141 : X_LUT4
    generic map(
      INIT => X"0001"
    )
    port map (
      ADR0 => key_in_2_IBUF_0,
      ADR1 => key_in_6_IBUF_0,
      ADR2 => key_in_0_IBUF_0,
      ADR3 => key_in_4_IBUF_0,
      O => N14_pack_1
    );
  Q_n0002_0_161 : X_LUT4
    generic map(
      INIT => X"0C00"
    )
    port map (
      ADR0 => VCC,
      ADR1 => CHOICE254_0,
      ADR2 => key_in_8_IBUF_0,
      ADR3 => N14,
      O => N120
    );
  N14_XUSED : X_BUF
    port map (
      I => N14_pack_1,
      O => N14
    );
  N14_YUSED : X_BUF
    port map (
      I => N120,
      O => N120_0
    );
  Ker151 : X_LUT4
    generic map(
      INIT => X"0001"
    )
    port map (
      ADR0 => key_in_1_IBUF_0,
      ADR1 => key_in_8_IBUF_0,
      ADR2 => key_in_9_IBUF_0,
      ADR3 => key_in_0_IBUF_0,
      O => N15
    );
  Q_n0002_3_1 : X_LUT4
    generic map(
      INIT => X"2800"
    )
    port map (
      ADR0 => N14,
      ADR1 => key_in_8_IBUF_0,
      ADR2 => key_in_9_IBUF_0,
      ADR3 => N16_0,
      O => Q_n0002(3)
    );
  N15_XUSED : X_BUF
    port map (
      I => N15,
      O => N15_0
    );
  Ker161 : X_LUT4
    generic map(
      INIT => X"0001"
    )
    port map (
      ADR0 => key_in_1_IBUF_0,
      ADR1 => key_in_3_IBUF_0,
      ADR2 => key_in_5_IBUF_0,
      ADR3 => key_in_7_IBUF_0,
      O => N16
    );
  N16_YUSED : X_BUF
    port map (
      I => N16,
      O => N16_0
    );
  Q_n000554 : X_LUT4
    generic map(
      INIT => X"0016"
    )
    port map (
      ADR0 => key_in_2_IBUF_0,
      ADR1 => key_in_8_IBUF_0,
      ADR2 => key_in_0_IBUF_0,
      ADR3 => key_in_6_IBUF_0,
      O => CHOICE272
    );
  CHOICE272_YUSED : X_BUF
    port map (
      I => CHOICE272,
      O => CHOICE272_0
    );
  Q_n000593 : X_LUT4
    generic map(
      INIT => X"005A"
    )
    port map (
      ADR0 => key_in_4_IBUF_0,
      ADR1 => VCC,
      ADR2 => key_in_6_IBUF_0,
      ADR3 => key_in_8_IBUF_0,
      O => CHOICE283_pack_1
    );
  Q_n000596 : X_LUT4
    generic map(
      INIT => X"0500"
    )
    port map (
      ADR0 => key_in_0_IBUF_0,
      ADR1 => VCC,
      ADR2 => key_in_2_IBUF_0,
      ADR3 => CHOICE283,
      O => CHOICE284
    );
  CHOICE283_XUSED : X_BUF
    port map (
      I => CHOICE283_pack_1,
      O => CHOICE283
    );
  CHOICE283_YUSED : X_BUF
    port map (
      I => CHOICE284,
      O => CHOICE284_0
    );
  Q_n0002_1_SW0 : X_LUT4
    generic map(
      INIT => X"FEE9"
    )
    port map (
      ADR0 => key_in_2_IBUF_0,
      ADR1 => key_in_3_IBUF_0,
      ADR2 => key_in_7_IBUF_0,
      ADR3 => key_in_6_IBUF_0,
      O => N23_pack_1
    );
  Q_n0002_1_Q : X_LUT4
    generic map(
      INIT => X"0002"
    )
    port map (
      ADR0 => N15_0,
      ADR1 => key_in_4_IBUF_0,
      ADR2 => key_in_5_IBUF_0,
      ADR3 => N23,
      O => Q_n0002(1)
    );
  N23_XUSED : X_BUF
    port map (
      I => N23_pack_1,
      O => N23
    );
  Q_n0002_2_SW0 : X_LUT4
    generic map(
      INIT => X"FEE9"
    )
    port map (
      ADR0 => key_in_4_IBUF_0,
      ADR1 => key_in_5_IBUF_0,
      ADR2 => key_in_6_IBUF_0,
      ADR3 => key_in_7_IBUF_0,
      O => N25_pack_1
    );
  Q_n0002_2_Q : X_LUT4
    generic map(
      INIT => X"0002"
    )
    port map (
      ADR0 => N15_0,
      ADR1 => key_in_3_IBUF_0,
      ADR2 => key_in_2_IBUF_0,
      ADR3 => N25,
      O => Q_n0002(2)
    );
  N25_XUSED : X_BUF
    port map (
      I => N25_pack_1,
      O => N25
    );
  clk_BUFGP_BUFG_BUF : X_CKBUF
    port map (
      I => clk,
      O => clk_BUFGP
    );
  NlwBlock_key_number_encoder_GND : X_ZERO
    port map (
      O => GND
    );
  NlwBlock_key_number_encoder_VCC : X_ONE
    port map (
      O => VCC
    );
  NlwBlockROC : X_ROC
    generic map (ROC_WIDTH => 100 ns)
    port map (O => GSR);
  NlwBlockTOC : X_TOC
    port map (O => GTS);

end Structure;