counter_tbw.ant

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--------------------------------------------------------------------------------
-- Copyright (c) 1995-2003 Xilinx, Inc.
-- All Right Reserved.
--------------------------------------------------------------------------------
--   ____  ____ 
--  /   /\/   / 
-- /___/  \  /    Vendor: Xilinx 
-- \   \   \/     Version : 7.1.04i
--  \   \         Application : ISE WebPACK
--  /   /         Filename : counter_tbw.ant
-- /___/   /\     Timestamp : Tue Mar 10 14:59:34 2009
-- \   \  /  \ 
--  \___\/\___\ 
--
--Command: 
--Design Name: counter_tbw
--Device: Xilinx
--

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_TEXTIO.ALL;
USE STD.TEXTIO.ALL;

ENTITY counter_tbw IS
END counter_tbw;

ARCHITECTURE testbench_arch OF counter_tbw IS
    FILE RESULTS: TEXT OPEN WRITE_MODE IS "D:\KSC\lab2\counter_tbw.ano";

    COMPONENT counter
        PORT (
            CLK : In std_logic;
            RESET : In std_logic;
            CE : In std_logic;
            LOAD : In std_logic;
            DIR : In std_logic;
            DIN : In std_logic_vector (3 DownTo 0);
            TC : Out std_logic;
            COUNT : InOut std_logic_vector (3 DownTo 0)
        );
    END COMPONENT;

    SIGNAL CLK : std_logic := '0';
    SIGNAL RESET : std_logic := '0';
    SIGNAL CE : std_logic := '0';
    SIGNAL LOAD : std_logic := '0';
    SIGNAL DIR : std_logic := '0';
    SIGNAL DIN : std_logic_vector (3 DownTo 0) := "0000";
    SIGNAL TC : std_logic := '0';
    SIGNAL COUNT : std_logic_vector (3 DownTo 0) := "0000";

    SHARED VARIABLE TX_ERROR : INTEGER := 0;
    SHARED VARIABLE TX_OUT : LINE;

    constant PERIOD : time := 100 ns;
    constant DUTY_CYCLE : real := 0.5;
    constant OFFSET : time := 0 ns;

    BEGIN
        UUT : counter
        PORT MAP (
            CLK => CLK,
            RESET => RESET,
            CE => CE,
            LOAD => LOAD,
            DIR => DIR,
            DIN => DIN,
            TC => TC,
            COUNT => COUNT
        );

        PROCESS    -- clock process for CLK
        BEGIN
            WAIT for OFFSET;
            CLOCK_LOOP : LOOP
                CLK <= '0';
                WAIT FOR (PERIOD - (PERIOD * DUTY_CYCLE));
                CLK <= '1';
                WAIT FOR (PERIOD * DUTY_CYCLE);
            END LOOP CLOCK_LOOP;
        END PROCESS;

        PROCESS    -- Annotation process for CLK
            VARIABLE TX_TIME : INTEGER := 0;

            PROCEDURE ANNOTATE_TC(
                TX_TIME : INTEGER
            ) IS
                VARIABLE TX_STR : String(1 to 4096);
                VARIABLE TX_LOC : LINE;
            BEGIN
                STD.TEXTIO.write(TX_LOC, string'("Annotate["));
                STD.TEXTIO.write(TX_LOC, TX_TIME);
                STD.TEXTIO.write(TX_LOC, string'(", TC, "));
                IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, TC);
                STD.TEXTIO.write(TX_LOC, string'("]"));
                TX_STR(TX_LOC.all'range) := TX_LOC.all;
                STD.TEXTIO.writeline(RESULTS, TX_LOC);
                STD.TEXTIO.Deallocate(TX_LOC);
            END;
        BEGIN
            WAIT for 1 fs;
            ANNOTATE_TC(0);
            WAIT for OFFSET;
            TX_TIME := TX_TIME + 0;
            ANNO_LOOP : LOOP
                --Rising Edge
                WAIT for 60 ns;
                TX_TIME := TX_TIME + 60;
                ANNOTATE_TC(TX_TIME);
                WAIT for 40 ns;
                TX_TIME := TX_TIME + 40;
            END LOOP ANNO_LOOP;
        END PROCESS;

        PROCESS
            BEGIN
                -- -------------  Current Time:  40ns
                WAIT FOR 40 ns;
                RESET <= '1';
                -- -------------------------------------
                -- -------------  Current Time:  140ns
                WAIT FOR 100 ns;
                RESET <= '0';
                -- -------------------------------------
                -- -------------  Current Time:  240ns
                WAIT FOR 100 ns;
                LOAD <= '1';
                DIN <= "0110";
                -- -------------------------------------
                -- -------------  Current Time:  340ns
                WAIT FOR 100 ns;
                LOAD <= '0';
                DIN <= "0000";
                -- -------------------------------------
                -- -------------  Current Time:  540ns
                WAIT FOR 200 ns;
                CE <= '1';
                -- -------------------------------------
                WAIT FOR 1560 ns;

                STD.TEXTIO.write(TX_OUT, string'("Total[]"));
                STD.TEXTIO.writeline(RESULTS, TX_OUT);
                ASSERT (FALSE) REPORT
                    "Success! Simulation for annotation completed"
                    SEVERITY FAILURE;
            END PROCESS;

    END testbench_arch;