counter.vhd

微波爐．．．．．．．．．．．．．．．．．．．．．．．．．．

--------------------------------------------------------------------------------
-- Company: 
-- Engineer:
--
-- Create Date:    10:48:02 02/09/09
-- Design Name:    
-- Module Name:    counter - Behavioral
-- Project Name:   
-- Target Device:  
-- Tool versions:  
-- Description:
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity counter is
    Port ( CLK : in std_logic;
           RESET : in std_logic;
           CE : in std_logic;
           LOAD : in std_logic;
           DIR : in std_logic;
           DIN : in std_logic_vector(3 downto 0);
--			  TC : out std_logic;
           COUNT : inout std_logic_vector(3 downto 0));
end counter;

architecture Behavioral of counter is
--signal temp_TC:	std_logic:='0';
begin

process (CLK,RESET,LOAD,DIN)
begin
	if RESET = '1' then
		COUNT <="0000";
--		TC<='0';
   else
		if  LOAD ='1'then
			COUNT <= DIN;
--			temp_TC<='0';
	 	elsif CLK ='1' and CLK'event then
				if CE='1' then
					if DIR ='1' then
							COUNT <= COUNT+1;
						else						
							COUNT <= COUNT-1;
					end if;
					else
--					  temp_TC<='0';
				end if;
	  	end if;
  	end if;
--	TC<=temp_TC;
end process;

end Behavioral;