microoven.syr

微波爐．．．．．．．．．．．．．．．．．．．．．．．．．．

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : microoven.ngr
Top Level Output File Name         : microoven
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 25

Macro Statistics :
# ROMs                             : 1
#      16x7-bit ROM                : 1
# Registers                        : 16
#      1-bit register              : 5
#      3-bit register              : 1
#      4-bit register              : 1
#      5-bit register              : 7
#      6-bit register              : 2
# Adders/Subtractors               : 9
#      5-bit adder                 : 7
#      6-bit adder                 : 2

Cell Usage :
# BELS                             : 219
#      GND                         : 1
#      INV                         : 12
#      LUT1                        : 22
#      LUT1_L                      : 14
#      LUT2                        : 11
#      LUT2_L                      : 4
#      LUT3                        : 14
#      LUT3_L                      : 12
#      LUT4                        : 41
#      LUT4_D                      : 2
#      LUT4_L                      : 12
#      MUXCY                       : 36
#      MUXF5                       : 1
#      VCC                         : 1
#      XORCY                       : 36
# FlipFlops/Latches                : 60
#      FDCE                        : 1
#      FDCPE                       : 4
#      FDE                         : 29
#      FDR                         : 12
#      FDRE                        : 11
#      FDSE                        : 3
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 24
#      IBUF                        : 14
#      OBUF                        : 10
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s50etq144-6 

 Number of Slices:                      82  out of    768    10%  
 Number of Slice Flip Flops:            60  out of   1536     3%  
 Number of 4 input LUTs:               132  out of   1536     8%  
 Number of bonded IOBs:                 25  out of    102    24%  
 Number of GCLKs:                        1  out of      4    25%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
u4/B:Q                             | NONE                   | 9     |
Clk                                | BUFGP                  | 46    |
u6/B:Q                             | NONE                   | 5     |
-----------------------------------+------------------------+-------+
INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: 8.983ns (Maximum Frequency: 111.321MHz)
   Minimum input arrival time before clock: 8.203ns
   Maximum output required time after clock: 9.532ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'u4/B:Q'
  Clock period: 5.302ns (frequency: 188.608MHz)
  Total number of paths / destination ports: 18 / 4
-------------------------------------------------------------------------
Delay:               5.302ns (Levels of Logic = 2)
  Source:            u3/COUNT_0 (FF)
  Destination:       u3/COUNT_3 (FF)
  Source Clock:      u4/B:Q rising
  Destination Clock: u4/B:Q rising

  Data Path: u3/COUNT_0 to u3/COUNT_3
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDCPE:C->Q           13   0.992   2.550  u3/COUNT_0 (u3/COUNT_0)
     LUT3_L:I1->LO         1   0.468   0.100  u3/COUNT__n0001<3>_SW0 (N230)
     LUT4_L:I1->LO         1   0.468   0.000  u3/COUNT__n0001<3> (u3/COUNT__n0001<3>)
     FDCPE:D                   0.724          u3/COUNT_3
    ----------------------------------------
    Total                      5.302ns (2.652ns logic, 2.650ns route)
                                       (50.0% logic, 50.0% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'Clk'
  Clock period: 8.983ns (frequency: 111.321MHz)
  Total number of paths / destination ports: 983 / 103
-------------------------------------------------------------------------
Delay:               8.983ns (Levels of Logic = 3)
  Source:            u4/counta_4 (FF)
  Destination:       u4/countd_2 (FF)
  Source Clock:      Clk rising
  Destination Clock: Clk rising

  Data Path: u4/counta_4 to u4/countd_2
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q              2   0.992   1.150  u4/counta_4 (u4/counta_4)
     LUT3_L:I0->LO         1   0.468   0.100  u4/_n0005_SW0 (N226)
     LUT4:I2->O           16   0.468   2.800  u4/_n0005 (u4/_n0005)
     LUT4:I1->O            6   0.468   1.850  u4/_n00251 (u4/_n0025)
     FDE:CE                    0.687          u4/countd_0
    ----------------------------------------
    Total                      8.983ns (3.083ns logic, 5.900ns route)
                                       (34.3% logic, 65.7% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'u6/B:Q'
  Clock period: 3.904ns (frequency: 256.148MHz)
  Total number of paths / destination ports: 4 / 4
-------------------------------------------------------------------------
Delay:               3.904ns (Levels of Logic = 1)
  Source:            u1/EN (FF)
  Destination:       u1/EN (FF)
  Source Clock:      u6/B:Q rising
  Destination Clock: u6/B:Q rising

  Data Path: u1/EN to u1/EN
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDCE:C->Q             5   0.992   1.720  u1/EN (u1/EN)
     LUT2:I1->O            1   0.468   0.000  u1/_n00021 (u1/_n0002)
     FDCE:D                    0.724          u1/EN
    ----------------------------------------
    Total                      3.904ns (2.184ns logic, 1.720ns route)
                                       (55.9% logic, 44.1% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'u6/B:Q'
  Total number of paths / destination ports: 19 / 12
-------------------------------------------------------------------------
Offset:              6.210ns (Levels of Logic = 3)
  Source:            Clear (PAD)
  Destination:       u1/EN (FF)
  Destination Clock: u6/B:Q rising

  Data Path: Clear to u1/EN
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             2   0.797   1.150  Clear_IBUF (Clear_IBUF)
     LUT4:I0->O            5   0.468   1.720  u1/_n0004 (u1/_n0004)
     LUT2:I1->O            1   0.468   0.920  u1/_n00161 (u1/_n0016)
     FDCE:CE                   0.687          u1/EN
    ----------------------------------------
    Total                      6.210ns (2.420ns logic, 3.790ns route)
                                       (39.0% logic, 61.0% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'u4/B:Q'
  Total number of paths / destination ports: 78 / 10
-------------------------------------------------------------------------
Offset:              8.203ns (Levels of Logic = 5)
  Source:            key8 (PAD)
  Destination:       u2/kload (FF)
  Destination Clock: u4/B:Q rising

  Data Path: key8 to u2/kload
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             8   0.797   2.050  key8_IBUF (key8_IBUF)
     LUT3:I2->O            1   0.468   0.920  u2/_n000593 (CHOICE704)
     LUT3:I0->O            1   0.468   0.920  u2/_n000596 (CHOICE705)
     LUT4:I0->O            1   0.468   0.920  u2/_n0005127 (CHOICE708)
     LUT3:I2->O            1   0.468   0.000  u2/_n0005161 (N198)
     FDE:D                     0.724          u2/kload
    ----------------------------------------
    Total                      8.203ns (3.393ns logic, 4.810ns route)
                                       (41.4% logic, 58.6% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'u4/B:Q'
  Total number of paths / destination ports: 28 / 7
-------------------------------------------------------------------------
Offset:              9.532ns (Levels of Logic = 2)
  Source:            u3/COUNT_0 (FF)
  Destination:       a (PAD)
  Source Clock:      u4/B:Q rising

  Data Path: u3/COUNT_0 to a
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDCPE:C->Q           13   0.992   2.550  u3/COUNT_0 (u3/COUNT_0)
     LUT4:I0->O            1   0.468   0.920  u5/Mrom_output_inst_lut4_01 (a_OBUF)
     OBUF:I->O                 4.602          a_OBUF (a)
    ----------------------------------------
    Total                      9.532ns (6.062ns logic, 3.470ns route)
                                       (63.6% logic, 36.4% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'u6/B:Q'
  Total number of paths / destination ports: 3 / 3
-------------------------------------------------------------------------
Offset:              6.744ns (Levels of Logic = 1)
  Source:            u1/temp_LED_0 (FF)
  Destination:       L_LED (PAD)
  Source Clock:      u6/B:Q rising

  Data Path: u1/temp_LED_0 to L_LED
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDSE:C->Q             2   0.992   1.150  u1/temp_LED_0 (u1/temp_LED_0)
     OBUF:I->O                 4.602          L_LED_OBUF (L_LED)
    ----------------------------------------
    Total                      6.744ns (5.594ns logic, 1.150ns route)
                                       (82.9% logic, 17.1% route)

=========================================================================
CPU : 3.39 / 3.64 s | Elapsed : 4.00 / 4.00 s
 
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Total memory usage is 88112 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :    0 (   0 filtered)
Number of infos    :    2 (   0 filtered)