microoven.syr

微波爐．．．．．．．．．．．．．．．．．．．．．．．．．．

Release 7.1.04i - xst H.42
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.
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--> Parameter xsthdpdir set to ./xst
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--> Reading design: microoven.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
  5) Advanced HDL Synthesis
     5.1) HDL Synthesis Report
  6) Low Level Synthesis
  7) Final Report
     7.1) Device utilization summary
     7.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : "microoven.prj"
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO

---- Target Parameters
Output File Name                   : "microoven"
Output Format                      : NGC
Target Device                      : xc2s50e-6-tq144

---- Source Options
Top Module Name                    : microoven
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
ROM Style                          : Auto
Mux Extraction                     : YES
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
Resource Sharing                   : YES
Multiplier Style                   : lut
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 100
Add Generic Clock Buffer(BUFG)     : 4
Register Duplication               : YES
Equivalent register Removal        : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : NO
Global Optimization                : AllClockNets
RTL Output                         : Yes
Write Timing Constraints           : NO
Hierarchy Separator                : /
Bus Delimiter                      : <>
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
Slice Utilization Ratio Delta      : 5

---- Other Options
lso                                : microoven.lso
Read Cores                         : YES
cross_clock_analysis               : NO
verilog2001                        : YES
safe_implementation                : No
Optimize Instantiated Primitives   : NO
tristate2logic                     : Yes
use_clock_enable                   : Yes
use_sync_set                       : Yes
use_sync_reset                     : Yes
enable_auto_floorplanning          : No

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "D:/ksc/micro_oven/PICunit.vhd" in Library work.
Architecture behavioral of Entity picunit is up to date.
Compiling vhdl file "D:/ksc/micro_oven/key_number_encoder.vhd" in Library work.
Architecture behavioral of Entity key_number_encoder is up to date.
Compiling vhdl file "D:/ksc/micro_oven/counter.vhd" in Library work.
Architecture behavioral of Entity counter is up to date.
Compiling vhdl file "D:/ksc/micro_oven/clkdiv2.vhd" in Library work.
Architecture behavioral of Entity clkdiv2 is up to date.
Compiling vhdl file "D:/ksc/micro_oven/clkdiv3.vhd" in Library work.
Architecture behavioral of Entity clkdiv3 is up to date.
Compiling vhdl file "D:/ksc/micro_oven/seven_segnment.vhd" in Library work.
Architecture behavioral of Entity seven_segnment is up to date.
Compiling vhdl file "D:/ksc/micro_oven/microoven.vhd" in Library work.
Architecture behavioral of Entity microoven is up to date.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <microoven> (Architecture <behavioral>).
Entity <microoven> analyzed. Unit <microoven> generated.

Analyzing Entity <PICunit> (Architecture <behavioral>).
Entity <PICunit> analyzed. Unit <PICunit> generated.

Analyzing Entity <key_number_encoder> (Architecture <behavioral>).
Entity <key_number_encoder> analyzed. Unit <key_number_encoder> generated.

Analyzing Entity <counter> (Architecture <behavioral>).
Entity <counter> analyzed. Unit <counter> generated.

Analyzing Entity <clkdiv2> (Architecture <behavioral>).
Entity <clkdiv2> analyzed. Unit <clkdiv2> generated.

Analyzing Entity <clkdiv3> (Architecture <behavioral>).
Entity <clkdiv3> analyzed. Unit <clkdiv3> generated.

Analyzing Entity <seven_segnment> (Architecture <behavioral>).
INFO:Xst:1561 - "D:/ksc/micro_oven/seven_segnment.vhd" line 69: Mux is complete : default of case is discarded
Entity <seven_segnment> analyzed. Unit <seven_segnment> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <seven_segnment>.
    Related source file is "D:/ksc/micro_oven/seven_segnment.vhd".
    Found 16x7-bit ROM for signal <output>.
    Summary:
	inferred   1 ROM(s).
Unit <seven_segnment> synthesized.


Synthesizing Unit <clkdiv3>.
    Related source file is "D:/ksc/micro_oven/clkdiv3.vhd".
    Found 5-bit adder for signal <$n0009> created at line 54.
    Found 5-bit adder for signal <$n0010> created at line 57.
    Found 1-bit register for signal <B>.
    Found 5-bit up counter for signal <counta>.
    Found 5-bit up counter for signal <countb>.
    Found 5-bit register for signal <countc>.
    Found 5-bit register for signal <countd>.
    Summary:
	inferred   2 Counter(s).
	inferred  11 D-type flip-flop(s).
	inferred   2 Adder/Subtractor(s).
Unit <clkdiv3> synthesized.


Synthesizing Unit <clkdiv2>.
    Related source file is "D:/ksc/micro_oven/clkdiv2.vhd".
    Found 6-bit adder for signal <$n0009> created at line 54.
    Found 6-bit adder for signal <$n0010> created at line 57.
    Found 1-bit register for signal <B>.
    Found 6-bit up counter for signal <counta>.
    Found 6-bit up counter for signal <countb>.
    Found 6-bit register for signal <countc>.
    Found 6-bit register for signal <countd>.
    Summary:
	inferred   2 Counter(s).
	inferred  13 D-type flip-flop(s).
	inferred   2 Adder/Subtractor(s).
Unit <clkdiv2> synthesized.


Synthesizing Unit <counter>.
    Related source file is "D:/ksc/micro_oven/counter.vhd".
    Found 4-bit down counter for signal <COUNT>.
    Summary:
	inferred   1 Counter(s).
Unit <counter> synthesized.


Synthesizing Unit <key_number_encoder>.
    Related source file is "D:/ksc/micro_oven/key_number_encoder.vhd".
    Found 1-bit register for signal <kload>.
    Found 4-bit register for signal <Qn>.
    Summary:
	inferred   5 D-type flip-flop(s).
Unit <key_number_encoder> synthesized.


Synthesizing Unit <PICunit>.
    Related source file is "D:/ksc/micro_oven/PICunit.vhd".
    Found 1-bit register for signal <Counter_Reset>.
    Found 1-bit register for signal <EN>.
    Found 3-bit register for signal <temp_LED>.
    Summary:
	inferred   5 D-type flip-flop(s).
Unit <PICunit> synthesized.


Synthesizing Unit <microoven>.
    Related source file is "D:/ksc/micro_oven/microoven.vhd".
Unit <microoven> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# ROMs                             : 1
 16x7-bit ROM                      : 1
# Adders/Subtractors               : 4
 5-bit adder                       : 2
 6-bit adder                       : 2
# Counters                         : 5
 4-bit down counter                : 1
 5-bit up counter                  : 2
 6-bit up counter                  : 2
# Registers                        : 11
 1-bit register                    : 5
 3-bit register                    : 1
 4-bit register                    : 1
 5-bit register                    : 2
 6-bit register                    : 2

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <microoven> ...

Optimizing unit <counter> ...

Optimizing unit <clkdiv3> ...

Optimizing unit <clkdiv2> ...

Optimizing unit <PICunit> ...

Optimizing unit <key_number_encoder> ...
Loading device for application Rf_Device from file '2s50e.nph' in environment c:/xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block microoven, actual ratio is 11.