seven_segnment.vhd

微波爐．．．．．．．．．．．．．．．．．．．．．．．．．．

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-- Company: 
-- Engineer:
--
-- Create Date:    10:50:02 02/09/09
-- Design Name:    
-- Module Name:    seven_segment - Behavioral
-- Project Name:   
-- Target Device:  
-- Tool versions:  
-- Description:
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity seven_segnment is
    Port (
		HEX : in std_logic_vector(3 downto 0);
		output : out std_logic_vector(6 downto 0)
	  );
end seven_segnment;

architecture Behavioral of seven_segnment is

begin
-- segment encoding
--      0
--     ---  
--  5 |   | 1
--     ---   <- 6
--  4 |   | 2
--     ---
--      3
-- 1= off 0= on
-- 0 1 2 3 4 5 6 
--"x x x x x x x" 
	process (HEX)
		begin
			case HEX is
				when x"0" => output <= "0000001";
				when x"1" => output <= "1001111";
				when x"2" => output <= "0010010";
				when x"3" => output <= "0000110";
				when x"4" => output <= "1001100";
				when x"5" => output <= "0100100";
				when x"6" => output <= "0100000";
				when x"7" => output <= "0001111";
				when x"8" => output <= "0000000";
				when x"9" => output <= "0000100";
				when x"A" => output <= "0001000";
				when x"B" => output <= "1100000";
				when x"C" => output <= "0110001";
				when x"D" => output <= "1000010";
				when x"E" => output <= "0110000";
				when x"F" => output <= "0111000";
				when others => output <= "1111111";
			end case;
	end process;


end Behavioral;