key_number_encoder.twr

微波爐．．．．．．．．．．．．．．．．．．．．．．．．．．

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Release 7.1.04i Trace H.42
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.

c:/xilinx/bin/nt/trce.exe -ise d:\ksc\lab2\micro_oven.ise -intstyle ise -e 3 -l
3 -s 6 -xml key_number_encoder key_number_encoder.ncd -o key_number_encoder.twr
key_number_encoder.pcf


Design file:              key_number_encoder.ncd
Physical constraint file: key_number_encoder.pcf
Device,speed:             xc2s50e,-6 (PRODUCTION 1.18 2005-01-22)
Report level:             error report

Environment Variable      Effect 
--------------------      ------ 
NONE                      No environment variables were set
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INFO:Timing:2698 - No timing constraints found, doing default enumeration.
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
   option. All paths that are not constrained will be reported in the
   unconstrained paths section(s) of the report.


Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Setup/Hold to clock clk
------------+------------+------------+------------------+--------+
            |  Setup to  |  Hold to   |                  |  Clock |
Source      | clk (edge) | clk (edge) |Internal Clock(s) |  Phase |
------------+------------+------------+------------------+--------+
key_en      |    1.563(R)|   -0.358(R)|clk_BUFGP         |   0.000|
key_in<0>   |    8.516(R)|   -6.107(R)|clk_BUFGP         |   0.000|
key_in<1>   |    7.809(R)|   -5.328(R)|clk_BUFGP         |   0.000|
key_in<2>   |    6.334(R)|   -4.179(R)|clk_BUFGP         |   0.000|
key_in<3>   |    7.246(R)|   -4.949(R)|clk_BUFGP         |   0.000|
key_in<4>   |    6.915(R)|   -3.822(R)|clk_BUFGP         |   0.000|
key_in<5>   |    7.119(R)|   -4.621(R)|clk_BUFGP         |   0.000|
key_in<6>   |    6.703(R)|   -4.309(R)|clk_BUFGP         |   0.000|
key_in<7>   |    8.136(R)|   -5.618(R)|clk_BUFGP         |   0.000|
key_in<8>   |    7.192(R)|   -3.860(R)|clk_BUFGP         |   0.000|
key_in<9>   |    6.920(R)|   -3.588(R)|clk_BUFGP         |   0.000|
------------+------------+------------+------------------+--------+

Clock clk to Pad
------------+------------+------------------+--------+
            | clk (edge) |                  |  Clock |
Destination | to PAD     |Internal Clock(s) |  Phase |
------------+------------+------------------+--------+
Qn<0>       |    6.465(R)|clk_BUFGP         |   0.000|
Qn<1>       |    6.381(R)|clk_BUFGP         |   0.000|
Qn<2>       |    6.430(R)|clk_BUFGP         |   0.000|
Qn<3>       |    6.465(R)|clk_BUFGP         |   0.000|
kload       |    6.465(R)|clk_BUFGP         |   0.000|
------------+------------+------------------+--------+

Analysis completed Tue Mar 10 15:32:22 2009
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Peak Memory Usage: 66 MB