_primary.vhd

VRILOG硬件语言 D主控触发器DFF_MC10131源代码

library verilog;
use verilog.vl_types.all;
entity DFF_Using_Behavior_vlg_sample_tst is
    port(
        Ce1             : in     vl_logic;
        Ce2             : in     vl_logic;
        Clr             : in     vl_logic;
        Set             : in     vl_logic;
        clk             : in     vl_logic;
        data_in         : in     vl_logic_vector(1 downto 0);
        sampler_tx      : out    vl_logic
    );
end DFF_Using_Behavior_vlg_sample_tst;