_primary.vhd

来自「VRILOG硬件语言 D主控触发器DFF_MC10131源代码」· VHDL 代码 · 共 10 行

library verilog;
use verilog.vl_types.all;
entity DFF_Using_Behavior_vlg_check_tst is
    port(
        q_out           : in     vl_logic_vector(1 downto 0);
        qb_out          : in     vl_logic_vector(1 downto 0);
        sampler_rx      : in     vl_logic
    );
end DFF_Using_Behavior_vlg_check_tst;