_primary.vhd

VRILOG硬件语言 D主控触发器DFF_MC10131源代码

library verilog;
use verilog.vl_types.all;
entity DFF_Using_Behavior is
    port(
        clk             : in     vl_logic;
        Ce1             : in     vl_logic;
        Ce2             : in     vl_logic;
        Clr             : in     vl_logic;
        Set             : in     vl_logic;
        q_out           : out    vl_logic_vector(1 downto 0);
        qb_out          : out    vl_logic_vector(1 downto 0);
        data_in         : in     vl_logic_vector(1 downto 0)
    );
end DFF_Using_Behavior;